search for: stackadjustment

Displaying 3 results from an estimated 3 matches for "stackadjustment".

2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...hain, VA.getLocReg(), Op.getOperand (i*2+1), - Flag); - Flag = Chain.getValue(1); - } + if (IsLastCallTailCall) { + IsLastCallTailCall = false; + SDOperand TailCall = GetTailCall(Op); + SDOperand TargetAddress = TailCall.getOperand(1); + SDOperand StackAdjustment = TailCall.getOperand(2); + assert ( ((TargetAddress.getOpcode() == ISD::Register && + cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX) || + TargetAddress.getOpcode() == ISD::TargetExternalSymbol || + TargetAddress.getOpcode()...
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...2+1), > - Flag); > - Flag = Chain.getValue(1); > - } > + if (IsLastCallTailCall) { > + IsLastCallTailCall = false; > + SDOperand TailCall = GetTailCall(Op); > + SDOperand TargetAddress = TailCall.getOperand(1); > + SDOperand StackAdjustment = TailCall.getOperand(2); > + assert ( ((TargetAddress.getOpcode() == ISD::Register && > + cast<RegisterSDNode>(TargetAddress)->getReg() == > X86::ECX) || > + TargetAddress.getOpcode() == > ISD::TargetExternalSymbol || > +...