Displaying 2 results from an estimated 2 matches for "st_d".
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2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
...ass<"Connex", [v128i16], 32,
(sequence "Wh%u", 0, 31)>;
I also added vector store and load instructions in the style of Mips MSA - see
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look
for "def ST_D", etc.
Note however that my vector unit has a separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uim...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...Class<"Connex", [v128i16], 32,
(sequence "Wh%u", 0, 31)>;
I also added vector store and load instructions in the style of Mips MSA - see
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look
for "def ST_D", etc.
Note however that my vector unit has a separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm...