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...order to do this i have made necessary changes in > X86ISelLowering.cpp. and rebuild llvm. then when i use the > command -view-dag-combine2-dags i get the required output in graph > but the following error on console: > > LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x > i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, > t12, undef:i64 > t7: v64i32 = add t6, t4 > t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x > i32>*)](align=16)(tbaa=<0x30c5438>)(deref...

...t; in order to do this i have made necessary changes in X86ISelLowering.cpp. >> and rebuild llvm. then when i use the command -view-dag-combine2-dags i >> get the required output in graph but the following error on console: >> >> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a >> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >> t7: v64i32 = add t6, t4 >> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceabl...

...IC_MOV_MEM>, EVEX; in x86instrinfo.td; when i build i got these instructions in X86GenInstrInfo. but still my instruction is not selected when i run input file in debug mode; getting following errors; ===== Instruction selection begins: BB#1 'vector.body' Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 Skipped scop...

...break it into 2 v64i32 instructions. in order to do this i have made necessary changes in X86ISelLowering.cpp. and rebuild llvm. then when i use the command -view-dag-combine2-dags i get the required output in graph but the following error on console: LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 t7: v64i32 = add t6, t4 t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64 t14:...

.... >>>> but still my instruction is not selected when i run input file in debug >>>> mode; getting following errors; >>>> >>>> >>>> ===== Instruction selection begins: BB#1 'vector.body' >>>> Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x >>>> i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 >>>> >>>> ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast >>>> ([65 x i32]* @c to <64 x i32>*)](align=16)...

...>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> ===== Instruction selection begins: BB#1 'vector.body' >>>>>>>>>>>>>> Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to >>>>>>>>>>>>>> <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, >>>>>>>>>>>>>> undef:i64 >>>>>>>>>>>>>> >>>>>...

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

...aLayout() return string "e-m:e-p:16:16-i32:32:32-i64:64-n32:32-S128". I also gave at the end of ConnexTargetLowering::ConnexTargetLowering() the following: ValueTypeActions.setTypeAction(MVT::i16, TypeLegal); to avoid errors like: Promote integer operand: t16: ch = store<ST256[inttoptr (i16 250 to <128 x i16>*)]> t13:1, t13, Constant:i16<250>, undef:i16 But even now it gives errors like: ISEL: Starting pattern match on root node: t16: ch = store<ST256[inttoptr (i16 250 to <128 x i16>*)]> t13:1, t13, Constant:i16<250>, undef:...

...ges in >>>> X86ISelLowering.cpp. and rebuild llvm. then when i use the >>>> command -view-dag-combine2-dags i get the required output in graph but >>>> the following error on console: >>>> >>>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* >>>> @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >>>> t7: v64i32 = add t6, t4 >>>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >>>> i32>*)](align=16)(tbaa=&...

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -