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llvm-stress crash
2017 Mar 14
3
llvm-stress crash
...a crash after Post-RA pseudo expansion, with machine verifier. A 128 bit register %vreg233:subreg_l32<def,read-undef> = LLCRMux %vreg119; GR128Bit:%vreg233 GRX32Bit:%vreg119 gets spilled: %vreg265:subreg_l32<def,read-undef> = LLCRMux %vreg119; GR128Bit:%vreg265 GRX32Bit:%vreg119 ST128 %vreg265, <fi#10>, 0, %noreg; mem:ST16[FixedStack10](align=8) GR128Bit:%vreg265 -> regalloc %R5L<def> = LLCRMux %R6L, %R4Q<imp-def> ST128 %R4Q<kill>, <fi#10>, 0, %noreg; mem:ST16[FixedStack10](align=8) -> pseudo expansion %R5L<def> = LLCR %R6L STG %R4D...