search for: ssub_1

...ter but later reading the 'S0' and 'S1' components separately. This is modeled with subregister operands which specify that only parts of a wider value are accessed. For example the register class of the 'DXX' registers supports subregisters calls 'ssub_0' and 'ssub_1' which would result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual register later. Typical operations are decomposing wider values or composing wide values with multiple smaller defs: Decomposing: %vreg1<def> = produce a 'D' value...

...'S1' components > separately. > This is modeled with subregister operands which specify that only > parts of a > wider value are accessed. For example the register class of the 'DXX' > registers supports subregisters calls 'ssub_0' and 'ssub_1' which > would > result in 'S4' and 'S5' getting used if 'D2' is assigned to the > virtual > register later. > > Typical operations are decomposing wider values or composing wide > values with > multiple smaller defs: &...

...'S1' components >> separately. >> This is modeled with subregister operands which specify that only parts >> of a >> wider value are accessed. For example the register class of the 'DXX' >> registers supports subregisters calls 'ssub_0' and 'ssub_1' which would >> result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual >> register later. >> >> Typical operations are decomposing wider values or composing wide values >> with >> multiple smaller defs: >> >&g...

...'S0' and 'S1' components separately. >> This is modeled with subregister operands which specify that only parts of a >> wider value are accessed. For example the register class of the 'DXX' >> registers supports subregisters calls 'ssub_0' and 'ssub_1' which would >> result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual >> register later. >> >> Typical operations are decomposing wider values or composing wide values with >> multiple smaller defs: >> >> Deco...

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

...= COPY %R25R24; WDREGS:%reg16384 // COPY A %reg16387<def> = COPY %reg16384:ssub_0; GPR8:%reg16387 WDREGS:%reg16384 // EXTRACT LO BYTE OF A %reg16388<def> = COPY %reg16385:ssub_0; GPR8:%reg16388 WDREGS:%reg16385 // EXTRACT LO BYTE OF B %reg16389<def> = COPY %reg16384:ssub_1; GPR8:%reg16389 WDREGS:%reg16384 // EXTRACT HI BYTE OF A %reg16390<def> = COPY %reg16385:ssub_1; GPR8:%reg16390 WDREGS:%reg16385 // EXTRACT HI BYTE OF B %reg16391<def> = ADDRdRr %reg16388, %reg16387<kill>, %SREG<imp-def>; GPR8:%reg16391,16388,16387 // ADD LO BYTES...

...th sub_32bit and sub_16bit have /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the /// sub_32bit sub-register. /// /// On the other hand, the ARM NEON lanes fully cover their registers: The /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. /// This is related to the CoveredBySubRegs property on register definitions. /// /// This function returns a bit mask of lanes that completely cover their /// sub-registers. More precisely, given: /// /// Covering = getCoveringLanes(); /// MaskA = getSubRegIndexLaneMask(Su...

The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are D0. The context here is an attempt to coalesce multiple loads/stores into fewer loads/stores