search for: sselevel

..."Enable AVX instructions", [FeatureSSE42, FeatureYMM, FeatureVEX]>; YMM, VEX and FMA are all separate features detectable through CPUID. The key question here is whether making X86AVX a boolean feature flag separate from X86SSELevel is reasonable. As I've been going along I've added feature flags for SSE4a and SSE5. These really do need to be separate feature flags because having SSE4a and/or SSE5 does not imply that you have SSE4.2 or SSE4.1. So they can't be part of the X86SSELevel scheme. Opinions on whet...

...nstructions", > [FeatureSSE42, FeatureYMM, > FeatureVEX]>; > > YMM, VEX and FMA are all separate features detectable through CPUID. > > The key question here is whether making X86AVX a boolean feature > flag separate > from X86SSELevel is reasonable. It sounds reasonable to me. > > > As I've been going along I've added feature flags for SSE4a and > SSE5. These > really do need to be separate feature flags because having SSE4a and/ > or SSE5 > does not imply that you have SSE4.2 or SSE4.1. So th...

...thing, just to play around, so I have not really put efforts into comments etc. yet. So when I build LLVM and try to run the pass with the following command: $ llc --debug -cgregalloc=cg <$HOME/cpptry/manyfuncs.bc I get the following error. Args: llc --debug -cgregalloc=cg Subtarget features: SSELevel 6, 3DNowLevel 0, 64bit 1 Pass ID not registered UNREACHABLE executed at /media/python/workspace/llvm/ lib/CodeGen/Passes.cpp:324! 0 llc 0x0000000001453dfe 1 llc 0x00000000014542fa 2 libpthread.so.0 0x00007f020b750cb0 3 libc.so.6 0x00007f020a99f425 gsignal + 53 4 l...

On Oct 31, 2012, at 1:41 PM, Madhusudan C.S <madhusudancs at gmail.com> wrote: > I have spent last 4 weeks trying to figure out how to implement > Interprocedural Register Allocation. I must admit that I was really > overwhelmed with LLVM's codebase while trying to figure this out :) > There is so much to know! I think I have reached a point where I > have some sort of

...forgotten when the Age that gave it birth returns again. -------------- next part -------------- llc -march=x86 -mcpu=CSE502 -filetype=asm -view-legalize-dags -debug blah.s Args: llc -march=x86 -mcpu=CSE502 -filetype=asm -view-legalize-dags -debug blah.s Features: CPU:CSE502 Subtarget features: SSELevel 0, 3DNowLevel 0, 64bit 1 MERGING MOSTLY EMPTY BLOCKS - BEFORE: for.body: ; preds = %for.cond br label %for.inc for.inc: ; preds = %for.body %2 = load i32* %i, align 4 %inc = add nsw i32 %2, 1 store i32 %inc,...

...lementptr inbounds i32* %a, i32 15 %15 = load i32* > %arrayidx28, align 4, !tbaa !1 %add29 = add nsw i32 %add27, %15 ret i32 > %add29}* > $ opt -S -slp-vectorizer -slp-vectorize-hor test.ll -debug -o test2.ll > > Features:+64bit,+sse2 > CPU:generic > > Subtarget features: SSELevel 3, 3DNowLevel 0, 64bit 1 > SLP: Analyzing blocks in foo. > > *test2.ll (IR after SLP vectorization) :* > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > &g...

...dd nsw i32 %add27, %15 store i32 %add29, i32* %sum, align 4, !tbaa !1 ret void } *IR after SLP vectorization with appropriate flags :* $ opt -S -slp-vectorizer -slp-vectorize-hor=1 -slp-vectorize-hor-store=1 test.ll -debug (I hope i am passing the args correctly to opt) Subtarget features: SSELevel 3, 3DNowLevel 0, 64bit 1 SLP: Analyzing blocks in foo. SLP: Found 1 stores to vectorize. SLP: Vectorizing a list of length = 2. ; ModuleID = 'test.ll' target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "x86_64-pc-linux-gnu" ; Function Att...

...nsw i32 %add25, %14 %arrayidx28 = getelementptr inbounds i32* %a, i32 15 %15 = load i32* %arrayidx28, align 4, !tbaa !1 %add29 = add nsw i32 %add27, %15 ret i32 %add29}* $ opt -S -slp-vectorizer -slp-vectorize-hor test.ll -debug -o test2.ll Features:+64bit,+sse2 CPU:generic Subtarget features: SSELevel 3, 3DNowLevel 0, 64bit 1 SLP: Analyzing blocks in foo. *test2.ll (IR after SLP vectorization) :* *target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"target triple = "x86_64-pc-linux-gnu"; Function Attrs: nou...

...rization with appropriate flags : > > > > > > $ opt -S -slp-vectorizer -slp-vectorize-hor=1 > -slp-vectorize-hor-store=1 test.ll -debug > > > > > > > > > (I hope i am passing the args correctly to opt) > > > > > > Subtarget features: SSELevel 3, 3DNowLevel 0, 64bit 1 > > > SLP: Analyzing blocks in foo. > > > SLP: Found 1 stores to vectorize. > > > SLP: Vectorizing a list of length = 2. > > > ; ModuleID = 'test.ll' > > > target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32...

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

...er-knl_o3.ll Features:+64bit,+sse2,+adx,+aes,+avx,+avx2,+avx512cd,+avx512er,+avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt CPU:knl Subtarget features: SSELevel 9, 3DNowLevel 1, 64bit 1 ********** Begin Constant Hoisting ********** ********** Function: foo ********** End Constant Hoisting ********** *** Interleaved Access Pass: foo CGP: Found local addrmode: [GV:@b] CGP: Found local addrmode: [GV:@c] CGP: Found local addrmode: [GV:@a] CGP: F...