Displaying 6 results from an estimated 6 matches for "ssefp".
Did you mean:
siefp
2004 Aug 06
0
[PATCH] Make SSE Run Time option. Add Win32 SSE code
> There is a big difference between SSE and SSEFP. The SSEFP means
> that the CPU supports the xmm registers. All Intel chips with SSE support
> do, however no current 32 bit AMD chips support the XMM registers. They
> will support the SSE instructions but not those registers. You are right
> about the SSE2 not being used.
I'm...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...of the SSE set.
If you read through AMD's processor detection guide
(PDF)
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
and go to section that shows the sample code for dealing with CPUID
support. (Starts about Page 37) It talks about the FEATURE_SSEFP support
which you have to query for. On the Atholon XP 2400+ that we have here,
that code does not detect the presence of that when run under Windows. The
same code on a Pentium 4 detects it just fine.
Here is an article which describes the K8 (Opteron and Atholon64) as
including the XMM regis...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
Jean-Marc,
There is a big difference between SSE and SSEFP. The SSEFP means
that the CPU supports the xmm registers. All Intel chips with SSE support
do, however no current 32 bit AMD chips support the XMM registers. They
will support the SSE instructions but not those registers. You are right
about the SSE2 not being used.
The AMD Opterons are the fi...
2004 Aug 06
6
[PATCH] Make SSE Run Time option.
...our
initial patch:
#define CPU_MODE_NONE 0
#define CPU_MODE_MMX 1 // Base Intel MMX x86
#define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions
#define CPU_MODE_SSE 4 // Intel Integer SSE instructions
#define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
#define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
#define CPU_MODE_SSE2 32 // Intel SSE2 instructions
#define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
Potential Additions include some of the ASM modes.
With the results that we found there is a relationship that looks like this:
3D...
2004 Aug 06
0
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...ead through AMD's processor detection guide
> (PDF)
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
>
> and go to section that shows the sample code for dealing with CPUID
> support. (Starts about Page 37) It talks about the FEATURE_SSEFP support
> which you have to query for. On the Atholon XP 2400+ that we have here,
> that code does not detect the presence of that when run under Windows. The
> same code on a Pentium 4 detects it just fine.
OK, I have gone though the doc and I think I understand. What they call
plain...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
All,
Attached is a patch that does two things. First it makes the use
of the current SSE code a run time option through the use
of speex_decoder_ctl() and speex_encoder_ctl
It does this twofold. First there is a modification to the configure.in
script which introduces a check based upon platform. It will compile in the
sse assembly if you are on an i?86 based platform by making a