search for: sse5

...[FeatureSSE42, FeatureYMM, FeatureVEX]>; YMM, VEX and FMA are all separate features detectable through CPUID. The key question here is whether making X86AVX a boolean feature flag separate from X86SSELevel is reasonable. As I've been going along I've added feature flags for SSE4a and SSE5. These really do need to be separate feature flags because having SSE4a and/or SSE5 does not imply that you have SSE4.2 or SSE4.1. So they can't be part of the X86SSELevel scheme. Opinions on whether AVX should be a separate flag or an SSELevel are welcome. Perhaps we need to retink the w...

...eparate features detectable through CPUID. > > The key question here is whether making X86AVX a boolean feature > flag separate > from X86SSELevel is reasonable. It sounds reasonable to me. > > > As I've been going along I've added feature flags for SSE4a and > SSE5. These > really do need to be separate feature flags because having SSE4a and/ > or SSE5 > does not imply that you have SSE4.2 or SSE4.1. So they can't be > part of the > X86SSELevel scheme. > > Opinions on whether AVX should be a separate flag or an SSELevel are &gt...

On 30-Apr-09, at 6:38 PM, Dan Gohman wrote: > On Apr 30, 2009, at 3:02 PM, David Greene wrote: >> As I've been going along I've added feature flags for SSE4a and >> SSE5. These >> really do need to be separate feature flags because having SSE4a and/ >> or SSE5 >> does not imply that you have SSE4.2 or SSE4.1. So they can't be >> part of the >> X86SSELevel scheme. >> [...] > > Offhand, I'd say SSE4a and SSE5 ought...

...); - show_flag(buffer, hardware->cpu.flags.nowprefetch, "3dnowprefetch ", false); - show_flag(buffer, hardware->cpu.flags.osvw, "osvw ", false); - show_flag(buffer, hardware->cpu.flags.ibs, "ibs ", false); - show_flag(buffer, hardware->cpu.flags.sse5, "sse5 ", false); - show_flag(buffer, hardware->cpu.flags.skinit, "skinit ", false); - show_flag(buffer, hardware->cpu.flags.wdt, "wdt ", false); - show_flag(buffer, hardware->cpu.flags.ida, "ida ", false); - show_flag(buffer, hardware-&g...

These patches fix a few compiler warnings. Tested on top of commit aee0dc5565711ef5be7c30fb5fc1c5f3f98db09f Jonathan Boeing (6): Use z width specifier when printing size_t variable pxe: fix truncation warning gpllib: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse com32/gpllib/dmi/dmi.c | 24 +++---

...AMD64 docs. it can be noted that most processors around now support SSE2, but not as many support newer (SSE3/SSSE3, SSE4, ...). note that Intel and AMD have had a split over the issue: Intel implements SSE3 and SSE4; AMD implements parts of SSE3 and SSE4, but not other parts; AMD is implementing SSE5, but it uses instructions which Intel does not use; ... so, SSE2 is fairly safe at this point, but much newer is an area with some peril... it would require checking documentation to know which operations are part of which subset. granted though, going too far down this route (especially if L...

Does anyone have any LLVM IR examples implementing things using the instructions for SSE, like complex arithmetic or 3D vector-matrix stuff? I'd like to have HLVM use them "under the hood" for some things but I cannot see all of the operations that I was expecting (e.g. dot product) and am not sure what works when (e.g. "Not all targets support all types however."). --

...000000x,edx=00xx000xx0xxx0xxxxxxxxxxxxxxxxxx' ] # up to leaf 0000_0003/8000_0004 # family 15 model 6 stepping 1 (Intel P4 Prescott, AMD K8) # disable POPCNT, SSE4.[12], SSSE3 # disable HTT # disable CMPLEGACY, SVM, EXTAPIC, ALTMOVCR8, ABM, SSE4a, MisAlignSSE, # 3DNOWPrefetch, OSVW, IBS, SSE5, SKINIT, WDT # disable 3DNOW, 3DNOWEXT, RDTSCP, Page1GB, FFXSR, MMXExt, MP # # Source: Cross-Vendor Migration # AMD Operating Systems Research Center # Uwe Dannowski Andre Przywara # {Firstname.Lastname}@amd.com # 2010 Advanced Micro Devices, Inc. All rights reserved. overlord3:~$ dmesg |...

...000000x,edx=00xx000xx0xxx0xxxxxxxxxxxxxxxxxx' ] # up to leaf 0000_0003/8000_0004 # family 15 model 6 stepping 1 (Intel P4 Prescott, AMD K8) # disable POPCNT, SSE4.[12], SSSE3 # disable HTT # disable CMPLEGACY, SVM, EXTAPIC, ALTMOVCR8, ABM, SSE4a, MisAlignSSE, # 3DNOWPrefetch, OSVW, IBS, SSE5, SKINIT, WDT # disable 3DNOW, 3DNOWEXT, RDTSCP, Page1GB, FFXSR, MMXExt, MP # # Source: Cross-Vendor Migration # AMD Operating Systems Research Center # Uwe Dannowski Andre Przywara # {Firstname.Lastname}@amd.com # 2010 Advanced Micro Devices, Inc. All rights reserved. overlord3:~$ dmesg |...