search for: sse4a

On 30-Apr-09, at 6:38 PM, Dan Gohman wrote: > On Apr 30, 2009, at 3:02 PM, David Greene wrote: >> As I've been going along I've added feature flags for SSE4a and >> SSE5. These >> really do need to be separate feature flags because having SSE4a and/ >> or SSE5 >> does not imply that you have SSE4.2 or SSE4.1. So they can't be >> part of the >> X86SSELevel scheme. >> [...] > > Offhand, I'd say SSE...

...[FeatureSSE42, FeatureYMM, FeatureVEX]>; YMM, VEX and FMA are all separate features detectable through CPUID. The key question here is whether making X86AVX a boolean feature flag separate from X86SSELevel is reasonable. As I've been going along I've added feature flags for SSE4a and SSE5. These really do need to be separate feature flags because having SSE4a and/or SSE5 does not imply that you have SSE4.2 or SSE4.1. So they can't be part of the X86SSELevel scheme. Opinions on whether AVX should be a separate flag or an SSELevel are welcome. Perhaps we need to ret...

...and FMA are all separate features detectable through CPUID. > > The key question here is whether making X86AVX a boolean feature > flag separate > from X86SSELevel is reasonable. It sounds reasonable to me. > > > As I've been going along I've added feature flags for SSE4a and > SSE5. These > really do need to be separate feature flags because having SSE4a and/ > or SSE5 > does not imply that you have SSE4.2 or SSE4.1. So they can't be > part of the > X86SSELevel scheme. > > Opinions on whether AVX should be a separate flag or an SS...

...me de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look like this: > > fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx > fxsr sse sse2 ht syscall nx lm nopl pni cx16...

...me de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look like this: > > fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx > fxsr sse sse2 ht syscall nx lm nopl pni cx16...

...ke this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_...

...ke this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_...

...e cx8 apic sep mtrr pge mca cmov pat pse36 clflush >>> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >>> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >>> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >>> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >>> >>> whereas in a (working) -cpu qemu64 guest, they look like this: >>> >>> fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx >>&g...

...e cx8 apic sep mtrr pge mca cmov pat pse36 clflush >>> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >>> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >>> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >>> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >>> >>> whereas in a (working) -cpu qemu64 guest, they look like this: >>> >>> fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx >>&g...

...tOperand(SrcRegNum)), CurByte, OS); CurOp = SrcRegNum + 1; break; } so here CurOp becomes 2. After this; it comes to; else { // If there is a remaining operand, it must be a trailing immediate. Emit it // according to the right size for the instruction. Some instructions // (SSE4a extrq and insertq) have two trailing immediates. while (CurOp != NumOps && NumOps - CurOp <= 2) { EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), CurByte, OS, Fixups); } here...

...c msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush >> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >> >> whereas in a (working) -cpu qemu64 guest, they look like this: >> >> fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx >> fxsr sse sse2 ht syscal...

...his windows laptop that I am testing on, I get these values: target_specific_cpu_args: skylake target_specific_features: +sse2,+cx16,-tbm,-avx512ifma,-avx512dq,-fma4,+prfchw,+bmi2,+xsavec,+fsgsbase,+popcnt,+aes,+xsaves,-avx512er,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-xop,+rdseed,-sse4a,-avx512bw,+clflushopt,+xsave,-avx512vl,-avx512cd,+avx,-rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4.1,+sse4.2,+avx2,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ssse3,+sgx,+cmov,-avx512vbmi,+movbe,+xsaveopt,-sha,+adx,-avx512pf,+sse3 It successfully creates a binary, but the binary when run crashes with: Unhand...

...- show_flag(buffer, hardware->cpu.flags.extapic, "extapic ", false); - show_flag(buffer, hardware->cpu.flags.cr8_legacy, "cr8_legacy ", false); - show_flag(buffer, hardware->cpu.flags.abm, "abm ", false); - show_flag(buffer, hardware->cpu.flags.sse4a, "sse4a ", false); - show_flag(buffer, hardware->cpu.flags.misalignsse, "misalignsse ", false); - show_flag(buffer, hardware->cpu.flags.nowprefetch, "3dnowprefetch ", false); - show_flag(buffer, hardware->cpu.flags.osvw, "osvw ", false); -...

...apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc art rep_good nopl nonstop_tsc extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb arat cpb hw_pstate npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold bmi1 bogomips : 7023.90 TLB size : 1536 4K pages clflush size : 64...

These patches fix a few compiler warnings. Tested on top of commit aee0dc5565711ef5be7c30fb5fc1c5f3f98db09f Jonathan Boeing (6): Use z width specifier when printing size_t variable pxe: fix truncation warning gpllib: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse com32/gpllib/dmi/dmi.c | 24 +++---

...o here CurOp becomes 2. >> >> After this; >> >> it comes to; >> else { >> // If there is a remaining operand, it must be a trailing immediate. >> Emit it >> // according to the right size for the instruction. Some instructions >> // (SSE4a extrq and insertq) have two trailing immediates. >> while (CurOp != NumOps && NumOps - CurOp <= 2) { >> EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), >> X86II::getSizeOfImm(TSFlags), >> getImmFixupKind(TSFlags), >>...

...on, I get these values: > > target_specific_cpu_args: skylake > > target_specific_features: +sse2,+cx16,-tbm,-avx512ifma,- > avx512dq,-fma4,+prfchw,+bmi2,+xsavec,+fsgsbase,+popcnt,+aes, > +xsaves,-avx512er,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,- > lwp,-xop,+rdseed,-sse4a,-avx512bw,+clflushopt,+xsave,- > avx512vl,-avx512cd,+avx,-rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4. > 1,+sse4.2,+avx2,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ > ssse3,+sgx,+cmov,-avx512vbmi,+movbe,+xsaveopt,-sha,+adx,-avx512pf,+sse3 > > > It successfully creates a binary, but the binary...

...t;>>> it comes to; >>>> else { >>>> // If there is a remaining operand, it must be a trailing >>>> immediate. Emit it >>>> // according to the right size for the instruction. Some >>>> instructions >>>> // (SSE4a extrq and insertq) have two trailing immediates. >>>> while (CurOp != NumOps && NumOps - CurOp <= 2) { >>>> EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), >>>> X86II::getSizeOfImm(TSFlags), >>>> getImmFixup...

...e and prints the assembler. I stumbled on this since the result of an actual calculation was wrong. So, it's not only the text version of the assembler also the machine assembler is wrong. When I execute the exploit program on an Intel KNL the following output is produced: CPU name = knl -sse4a,-avx512bw,cx16,-tbm,xsave,-fma4,-avx512vl,prfchw,bmi2,adx,-xsavec,fsgsbase,avx,avx512cd,avx512pf,-rtm,popcnt,fma,bmi,aes,rdrnd,-xsaves,sse4.1,sse4.2,avx2,avx512er,sse,lzcnt,pclmul,avx512f,f16c,ssse3,mmx,-pku,cmov,-xop,rdseed,movbe,-hle,xsaveopt,-sha,sse2,sse3,-avx512dq, Assembly: .text .f...

...lse) ret i64 %t3 } declare i64 @llvm.objectsize.i64( i8*, i1) declare noalias i8* @malloc(i64) #1 declare void @bar1(i8*) #2 declare void @bar2(i8*) #2 declare i32 @bar3(i8*) #2 attributes #0 = { nounwind ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" } attributes #1 = { nounwind "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-...