search for: ssaregmap

...really nice is a method to add Value*. So, I would write: BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); and depending on whether the passed Value* is contant or instruction, the add method would either add immediate constant or allocate/get new virtual register. 2. Why SSARegMap is called this way. As far as I can see, it's does not implement any mapping, it simply allocates registers given a register class. 3. Maybe, the allocation of virtual registers for Value* should be made more reusable. The X86 backend has the code for that in getReg method in InstSelectSimp...

...code will work fine, but will be ugly and slow. As the second step, when the selector is basically working, you can add cases to handle these. Taken to a limit you'll get something as complex as the X86 InstSelectSimple (which as someone mentioned, is not really simple anymore). > 2. Why SSARegMap is called this way. As far as I can see, it's does not > implement any mapping, it simply allocates registers given a register class. You're right, it currently just keeps track of the register class for each virtual register. Eventually it will keep track of which machine instruction...

Evan, Can you explain the basic mechanics of the live interval splitting code? Is it all in LiveIntervalAnalysis.cpp under addIntervalsForSpills and child routines? What is it trying to do? Also, in the ancient subregister coalescing code, there used to be an update of the SSARegMap to point subregisters to the superregister they were coalesced to (IIRC). That has since gone away. I used to use that in my code to return the correct live interval for a virtual register in the case where a subregister extract was coalesced. That information appears to now be in RegSubIdxMap,...

How do I get the TargetRegisterClass for a physical register? SSARegMap::getRegClass only works for virtual registers. -Dave

...l registers. Ok, you could add a method to LiveVariables that returns VirtRegInfo.size(). The virtual registers are defined by the range: [MRegisterInfo::FirstVirtualRegister, MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] Alternatively, the same information can be obtained from the SSARegMap for the function: given a MachineFunction, use something like: NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; These also start from MRegisterInfo::FirstVirtualRegister. > But LiveIntervalAnalysis.h is not in > "include/llvm/CodeGen", so I have to either include it by: >...

One of my pass requires LiveIntervals to build the interference graph, because LiveVariables do not provide an interface to iterate through all viritual registers. But LiveIntervalAnalysis.h is not in "include/llvm/CodeGen", so I have to either include it by: #include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h" or point my project include path to

...is, when an interval is spilled, it introduce a single reload per basic block and retarget all the uses to use the result of the single reload. It does not (yet) split intra-bb intervals. > > Also, in the ancient subregister coalescing code, there used to be > an update > of the SSARegMap to point subregisters to the superregister they were > coalesced to (IIRC). That has since gone away. I used to use that > in my > code to return the correct live interval for a virtual register in > the case > where a subregister extract was coalesced. Right. That has been re...

...introduce a single reload per > basic block and retarget all the uses to use the result of the single > reload. It does not (yet) split intra-bb intervals. Ah, got it. Thanks. > > Also, in the ancient subregister coalescing code, there used to be > > an update > > of the SSARegMap to point subregisters to the superregister they were > > coalesced to (IIRC). That has since gone away. I used to use that > > in my > > code to return the correct live interval for a virtual register in > > the case > > where a subregister extract was coalesced. &gt...

...ould add a method to LiveVariables that returns > VirtRegInfo.size(). The virtual registers are defined by the range: > [MRegisterInfo::FirstVirtualRegister, > MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] > > Alternatively, the same information can be obtained from the SSARegMap for > the function: given a MachineFunction, use something like: > > NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; > > These also start from MRegisterInfo::FirstVirtualRegister. I'm not sure if these two methods work because after the live intervals are joined, some vir...

..., ope FP_ReadOnlyRC :$src), "mov $dest, $src">; In the instruction selector, SDOperand::getValueType() always returns 'MVT::packed' for all operands. I cannot distinguish between GeneralPurposeRC, INT_ReadOnlyRC, FP_ReadOnlyRC. But a correct register class is necessary for SSARegMap to create a virtual register. 2005/7/22, Misha Brukman <brukman at cs.uiuc.edu>: > On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > > I' have three set of registers - read-only regs, general purpose regs > > (read and write), and write-only regs...

...he first place. I though about something code which create immediate operand from constant and virtual register from Value* which really points to Instruction*. There should also be some mechanism to avoid creating two immediate operands, if target does not allow that. > > 2. Why SSARegMap is called this way. As far as I can see, it's does not > > implement any mapping, it simply allocates registers given a register > > class. > > You're right, it currently just keeps track of the register class for each > virtual register. Eventually it will keep track...

Hello. I am making a backend for a virtual machine. But it does assume infinite number of virtual registers unlike those of usual machines. In this case, how can I implement this? Would you mind telling me some tips? Thank you so much. Seung Jae Lee

Take a look at getPhysicalRegisterRegClass( const MRegisterInfo *MRI, MVT::ValueType VT, unsigned reg) in ScheduleDAG.cpp. -- Christopher Lamb On Jun 18, 2007, at 4:52 PM, David A. Greene wrote: > How do I get the TargetRegisterClass for a physical register? > SSARegMap::getRegClass only works for virtual registers. > > -Dave > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/list...

Chris Lattner wrote: > On Sat, 13 May 2006, Vladimir Prus wrote: >> in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' >> parameter, that is not documented. >> >> Can somebody explain what does it mean? > > Basically, it gives the target more information about the spill. In > particular, it specifies the register class to use

...sterClass<packed, 128, [F0, F1]>; ... > In the instruction selector, SDOperand::getValueType() always returns > 'MVT::packed' for all operands. I cannot distinguish between > GeneralPurposeRC, INT_ReadOnlyRC, FP_ReadOnlyRC. But a correct > register class is necessary for SSARegMap to create a virtual > register. What does a 'read only' register mean? Is it a constant (e.g. returns 1.0)? Otherwise, how can it be a useful value? -Chris > > > 2005/7/22, Misha Brukman <brukman at cs.uiuc.edu>: >> On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu...

...o LiveVariables that returns >> VirtRegInfo.size(). The virtual registers are defined by the range: >> [MRegisterInfo::FirstVirtualRegister, >> MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] >> >> Alternatively, the same information can be obtained from the SSARegMap for >> the function: given a MachineFunction, use something like: >> >> NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; >> >> These also start from MRegisterInfo::FirstVirtualRegister. > > I'm not sure if these two methods work because after the live &gt...

...1,6 +21,8 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/CodeGen/RegisterAllocator.h" +#include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetMachine.h" @@ -47,7 +49,8 @@ static unsigned numIterations = 0; static unsigned numIntervals = 0; - struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass { + struct VISIBILITY_HIDDEN...

On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > I' have three set of registers - read-only regs, general purpose regs > (read and write), and write-only regs. How should I partition them > into different RegisterClasses so that I can easy define the > instruction? [snip] > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, >

On Jul 11, 2007, at 11:39 AM, David Greene wrote: > On Wednesday 11 July 2007 12:41, Tanya M. Lattner wrote: > >> I think the coalescer should be flexible enough to be run >> independent of >> the register allocator. For example, you may want to expose the >> copies >> induced by transforming out of SSA to the scheduler. If the >> scheduler is

Hi, everyone. I' have three set of registers - read-only regs, general purpose regs (read and write), and write-only regs. How should I partition them into different RegisterClasses so that I can easy define the instruction? All RegisterClasses must be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def