search for: sregs

Add GS base to the HVM VCPU context returned by xc_vcpu_getcontext() Signed-off-by: Aravindh Puthiyaparambil <aravindh@virtuata.com> diff -r e62ab14d44af -r babbb3e0f4d3 xen/arch/x86/domctl.c --- a/xen/arch/x86/domctl.c Fri Apr 20 11:36:02 2012 -0700 +++ b/xen/arch/x86/domctl.c Fri Apr 20 17:55:49 2012 -0700 @@ -1592,6 +1592,12 @@ void arch_get_info_guest(struct vcpu *v,

..._edge, %entry %sum.0.lcssa = phi i32 [ %8, %for.cond.for.end_crit_edge ], [ 0, %entry ] ret i32 %sum.0.lcssa } The emitted blocks are: Function Live Ins: %R0 in %vreg2 BB#0: derived from LLVM BB %entry Live Ins: %R0 %vreg2<def> = COPY %R0; IntRegs:%vreg2 %vreg3<def> = MV 0; SRegs:%vreg3 CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 BR_cc <BB#2>, 20, %FLAG<imp-use,kill> BR <BB#1> Successors according to CFG: BB#1(20) BB#2(12) BB#1: derived from LLVM BB %for.cond.for.end_crit_edge Predec...

Hello list, I have a linear regression ctl <- c(4.17,5.58,5.18,6.11,4.50,4.61,5.17,4.53,5.33,5.14) trt <- c(4.81,4.17,4.41,3.59,5.87,3.83,6.03,4.89,4.32,4.69) group <- gl(2,10,20, labels=c("Ctl","Trt")) weight <- c(ctl, trt) reg <- lm(weight ~ group) sreg <- summary(reg) and I would like to dump exactly what I see on the console with

...gt; ret i32 %sum.0.lcssa >> } >> >> >> The emitted blocks are: >> Function Live Ins: %R0 in %vreg2 >> >> BB#0: derived from LLVM BB %entry >> Live Ins: %R0 >> %vreg2<def> = COPY %R0; IntRegs:%vreg2 >> %vreg3<def> = MV 0; SRegs:%vreg3 >> CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 >> %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 >> BR_cc <BB#2>, 20, %FLAG<imp-use,kill> >> BR <BB#1> >> Successors according to CFG: BB#1(20) BB#2(12) >> >> BB#1...

Hi all, For loads and stores i want to extract information about the number of indices accessed. For instance: struct S {int X, int *Y}; __global__ void kernel(int *A, int **B, struct S) {   int x = A[..][..]; // -> L: A[..][..]   int y = *B[2];   // -> L: B[0][2]   int z = S.y[..];  // -> L: S.1[..]   // etc.. } I am performing some preprocessing on IR to: 1. Move constant

...vCPU index and the event id:: + + struct kvmi_event { + __u16 size; + __u16 vcpu; + __u8 event; + __u8 padding[3]; + struct kvmi_event_arch arch; + } + +On x86 the structure looks like this:: + + struct kvmi_event_arch { + __u8 mode; + __u8 padding[7]; + struct kvm_regs regs; + struct kvm_sregs sregs; + struct { + __u64 sysenter_cs; + __u64 sysenter_esp; + __u64 sysenter_eip; + __u64 efer; + __u64 star; + __u64 lstar; + __u64 cstar; + __u64 pat; + __u64 shadow_gs; + } msrs; + }; + +It contains information about the vCPU state at the time of the event. + +The reply to e...

...>>>> The emitted blocks are: >>>> Function Live Ins: %R0 in %vreg2 >>>> >>>> BB#0: derived from LLVM BB %entry >>>> Live Ins: %R0 >>>> %vreg2<def> = COPY %R0; IntRegs:%vreg2 >>>> %vreg3<def> = MV 0; SRegs:%vreg3 >>>> CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 >>>> %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 >>>> BR_cc <BB#2>, 20, %FLAG<imp-use,kill> >>>> BR <BB#1> >>>> Successors according to CFG: BB#...

I'm confused as to the logic used in the register scavenger when it cannot find a free register. I would think that it would want to free up the emergency spill slot immediately after it's use, because otherwise there is a chance of needing to use the emergency slot again and not be able to. Instead it tries to restore it only right before register it is freeing up. Maybe I'm

Hello, some months ago i wrote to the mailing list asking some questions about register pairing, i've been experimenting several things with the help i got back then. Some background first: this issue is for a backend for an 8bit microcontroller with only 8bit regs, however it has a few 16bit instructions that only work with fixed register pairs, so it doesnt allow all combinations of regs.

...n 0; } +void kvm_arch_vcpu_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + __get_regs(vcpu, regs); +} + static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { vcpu->arch.emulate_regs_need_sync_from_vcpu = true; @@ -8710,6 +8715,11 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, return 0; } +void kvm_arch_vcpu_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) +{ + __get_sregs(vcpu, sregs); +} + int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { diff --git a/include/linux/kvm_host.h b/in...

...gt;>>>> Function Live Ins: %R0 in %vreg2 >>>>>> >>>>>> BB#0: derived from LLVM BB %entry >>>>>> Live Ins: %R0 >>>>>> %vreg2<def> = COPY %R0; IntRegs:%vreg2 >>>>>> %vreg3<def> = MV 0; SRegs:%vreg3 >>>>>> CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2 >>>>>> %vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3 >>>>>> BR_cc <BB#2>, 20, %FLAG<imp-use,kill> >>>>>> BR <BB#1> >>>>&...

I tried to manually assign each of 3 arrays a unique TBAA node. But it does not seem to help: alias analysis still considers arrays as may-alias, which most likely prevents the desired optimization. Below is the sample code with TBAA metadata inserted. Could you please suggest what might be wrong with it? Many thanks, - D. marcusmae at M17xR4:~/forge/llvm$ opt -time-passes -enable-tbaa -tbaa

Hi Ees, SCEV Delinearization is the closest I know. But it has its problems. Well for one your expression should be SCEVable. But more importantly, SCEV Delinearization is trying to deduce something that is high-level (actually source-level) from a low-level IR in which a lot of this info has been lost. So, since there's not a 1-1 mapping from high-level code to LLVM IR, going backwards will

Hi Reed, the register scavenger (RS) also keeps track of live registers. This way it "knows" that the register that was spilled/restored far apart is available. Let say you had the following code. You need to find a register to keep vreg1 and vreg2 in. R1 = .... // <- RS current liveness state; we have called RS->forward(It) where It points to here vreg1 = add SP, 1000 ... =

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to get kvm_regs and kvm_sregs structures, plus the list of struct kvm_msrs. Signed-off-by: Mihai Don?u <mdontu at bitdefender.com> Co-developed-by: Adalbert Laz?r <alazar at bitdefender.com> Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com> --- Documentation/virt/kvm/kvmi.rst | 42 +++++...

Dear all, Attached notunrolled.ll is a module containing reduction kernel. What I'm trying to do is to unroll it in such way, that partial reduction on unrolled iterations would be performed on register, and then stored to memory only once. Currently llvm's unroller together with all standard optimizations produce code, which stores value to memory after every unrolled iteration, which is

Hello all, I am working on adding atomics support to the AVR backend. Because the target can only have one core, it is sufficient to: - Save the status register - Disable interrupts - Do the nonatomic LOAD/STORE/SWAP/ADD - Restore the status register I’d really like to be able to do this at the IR level. What I want to do is write a custom lowering hook to convert ISD::ATOMIC_LOAD

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to get kvm_regs and kvm_sregs structures, plus a list of struct kvm_msrs from a specific vCPU. While the kvm_regs and kvm_sregs structures are included with every event, this command allows reading any MSR and can be used as a quick way to read the state of any vCPU. Signed-off-by: Mihai Don?u <mdontu at bitdefender.com&gt...

Full_Name: Andrew Manners Version: 2.5.1 OS: windows xp prof 2003 Submission from: (NULL) (130.102.0.177) To whom it may concern, I'm trying to get an ANOVA table within survreg but it always produces NA's in the p-value, regardless of the data set. The data set below comes from Tableman and Kim 2004. I had the same problem on a number of my own data sets. I searched the R site for

...mi.c @@ -5,8 +5,61 @@ * Copyright (C) 2019-2020 Bitdefender S.R.L. */ +#include "linux/kvm_host.h" +#include "x86.h" #include "../../../virt/kvm/introspection/kvmi_int.h" +static unsigned int kvmi_vcpu_mode(const struct kvm_vcpu *vcpu, + const struct kvm_sregs *sregs) +{ + unsigned int mode = 0; + + if (is_long_mode((struct kvm_vcpu *) vcpu)) { + if (sregs->cs.l) + mode = 8; + else if (!sregs->cs.db) + mode = 2; + else + mode = 4; + } else if (sregs->cr0 & X86_CR0_PE) { + if (!sregs->cs.db) + mode = 2; + else + mode = 4; +...