search for: srcvt

Displaying 8 results from an estimated 8 matches for "srcvt".

2011 Feb 07
2
[LLVMdev] Promoting i16 load to i32
...get this failed assertion: llc: LegalizeDAG.cpp:1309: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `0 && "This action is not supported yet!"' failed. I initially expected the if statement on line 1191 (in my copy), `if (SrcWidth != SrcVT.getStoreSizeInBits()` to catch my i16 promotion case - but it doesn't because SrcVT.getSizeInBits() and SrcVT.getStoreSizeInBits() equals 16 with SrcVT == MVT::i16. I'd appreciate any pointers in the right direction. Thank you, Alex
2015 Mar 04
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
...y an > extension". So, the "EXT" part is probably irrelevant here, if that's > what's bugging you ;) Nevermind, grepping around shows this is specifically about ISD::EXTLOAD, in LegalizeLoadOps (LegalizeDAG.cpp). There's some code above, with an "isTypeLegal(SrcVT)" check, that tries to turn an EXTLOAD into LOAD+[SZ]EXT. I'm guessing that on your target, both the EXTLOAD from i8 and the i8 type are illegal? In that case, again, I don't know how one could legalize this. -Ahmed
2015 Mar 05
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
...part is probably irrelevant here, if that's >> > what's bugging you ;) >> >> Nevermind, grepping around shows this is specifically about >> ISD::EXTLOAD, in LegalizeLoadOps (LegalizeDAG.cpp). >> >> There's some code above, with an "isTypeLegal(SrcVT)" check, that >> tries to turn an EXTLOAD into LOAD+[SZ]EXT. I'm guessing that on your >> target, both the EXTLOAD from i8 and the i8 type are illegal? >> >> In that case, again, I don't know how one could legalize this. >> >> -Ahmed > >
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...ave SSE, these could be more efficient, by using movd/movq. @@ -4608,8 +4612,14 @@ SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); + return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); +} +SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, + SDValue StackSlot, + SelectionDAG &DAG) { // Build the FILD + DebugLoc dl = Op.getDebugLoc(); SDVTList Tys;...
2015 Mar 04
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
Ahmed, Yes, this is the case, I'm sure many other 'spots' in DAGCombiner use this same check or use a similar check with LegalOperations. It just seems like bad form to have core code that generates an illegal node that legalization cannot seem to handle, unless I'm missing something, which is entirely possible. Potentially we are using the wrong LegalAction, though each I've
2014 Nov 03
8
[LLVMdev] [PATCH] Protection against stack-based memory corruption errors using SafeStack
...+ /// in some non-standard address space, and populates the address space and + /// offset as appropriate. + virtual bool getUnsafeStackPtrLocation(unsigned &AddressSpace, + unsigned &Offset) const; + SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const; diff --git a/lib/Transforms/IPO/Inliner.cpp b/lib/Transforms/IPO/Inliner.cpp index 4ce6dfe..e0695d2 100644 --- a/lib/Transforms/IPO/Inliner.cpp +++ b/lib/Transforms/IPO/Inliner.cpp @@ -93,7 +93,8 @@ static voi...