search for: srcrc

Displaying 13 results from an estimated 13 matches for "srcrc".

2011 Mar 22
0
[LLVMdev] sitofp inst selection in x86/AVX target [PR9473]
...and move existing VCVTSI2SD definition from isAsmParserOnly = 0 into isAsmParserOnly = 1 block so that existing VCVTSI2SD definition takes effect only in asm parser. Example solution is as follows. lib/Target/X86/x86InstrSSE.td ... multiclass sse12_vcvt_avx_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, string asm> { def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, [(set DstRC:$dst, (OpNode SrcRC:$src))]>; def rm : SI<o...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...s differ, the resulting code is wrong. I've managed to get around this by inserting a COPY in TailDuplication but I don't know what the proper fix is to this. In TailDuplicatePass::ProcessPHI: const TargetRegisterClass *RC = MRI->getRegClass(DefReg); + const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg); + + // If the register class of the PHI src is wider than the PHI def + // then we can't just use PHI src instead of PHI def in the cloned + // instruction. Instead we insert a copy, copying the PHI src to a + // register of the wanted register class. + if (!...
2009 Apr 28
1
[LLVMdev] Register class intersection
...s divided by B.SpillAlignment This would introduce two new subclass chains: RFP80 subclass of RFP64 subclass of RFP32 VR128 subclass of FR64 Define intersection as described above: intersection(A, B) = max { X | X subclass-eq A, X subclass-eq B } The coalescer can then use NewRC = intersection(SrcRC, DstRC). This gives the same result for the existing targets, and it works correctly for blackfin and other future targets. The subclass relation can be seen as adding constraints on a virtual register. If A is a subclass of B, it is always legal to change a virtual register class from B t...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...a TON of false positives). Where does II come from? From the snippet, I am guessing it is the instruction that uses NewVReg, i.e., you are checking that the class for NewVReg matches the class for NewVReg… which by construction is always true! You want to check "common subclass” of DstRC and SrcRC. Cheers, Q. > > Thanks. > > On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote:...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
.... > > Where does II come from? > From the snippet, I am guessing it is the instruction that uses NewVReg, i.e., you are checking that the class for NewVReg matches the class for NewVReg… which by construction is always true! > > You want to check "common subclass” of DstRC and SrcRC. > > Cheers, > Q. > >> >> Thanks. >> >> On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >>> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com &lt...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...; From the snippet, I am guessing it is the instruction that uses NewVReg, >>> i.e., you are checking that the class for NewVReg matches the class for >>> NewVReg… which by construction is always true! >>> >>> You want to check "common subclass” of DstRC and SrcRC. >>> >>> Cheers, >>> Q. >>> >>> >>> Thanks. >>> >>> On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <qcolombet at apple.com> >>> wrote: >>> >>>> >>>> On Aug 22, 2015, at 9:10 AM...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...Where does II come from? >> From the snippet, I am guessing it is the instruction that uses NewVReg, i.e., you are checking that the class for NewVReg matches the class for NewVReg… which by construction is always true! >> >> You want to check "common subclass” of DstRC and SrcRC. >> >> Cheers, >> Q. >> >>> >>> Thanks. >>> >>> On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >>> >>>> On Aug 22, 2015, at 9:10 AM, R...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...t;>>>> NewVReg, i.e., you are checking that the class for NewVReg matches the >>>>>>>> class for NewVReg… which by construction is always true! >>>>>>>> >>>>>>>> You want to check "common subclass” of DstRC and SrcRC. >>>>>>>> >>>>>>>> Cheers, >>>>>>>> Q. >>>>>>>> >>>>>>>> >>>>>>>> Thanks. >>>>>>>> >>>>>>>> On Mon, Aug 24,...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...t;> NewVReg, i.e., you are checking that the class for NewVReg matches the >>>>>>>>> class for NewVReg… which by construction is always true! >>>>>>>>> >>>>>>>>> You want to check "common subclass” of DstRC and SrcRC. >>>>>>>>> >>>>>>>>> Cheers, >>>>>>>>> Q. >>>>>>>>> >>>>>>>>> >>>>>>>>> Thanks. >>>>>>>>> >>>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...eg, i.e., you are checking that the class for NewVReg matches the >>>>>>>>>> class for NewVReg… which by construction is always true! >>>>>>>>>> >>>>>>>>>> You want to check "common subclass” of DstRC and SrcRC. >>>>>>>>>> >>>>>>>>>> Cheers, >>>>>>>>>> Q. >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Thanks. >>>>>>>>&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...u are checking that the class for NewVReg matches the >>>>>>>>>>> class for NewVReg… which by construction is always true! >>>>>>>>>>> >>>>>>>>>>> You want to check "common subclass” of DstRC and SrcRC. >>>>>>>>>>> >>>>>>>>>>> Cheers, >>>>>>>>>>> Q. >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Thanks. >>&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ng that the class for NewVReg matches the >>>>>>>>>>>> class for NewVReg… which by construction is always true! >>>>>>>>>>>> >>>>>>>>>>>> You want to check "common subclass” of DstRC and SrcRC. >>>>>>>>>>>> >>>>>>>>>>>> Cheers, >>>>>>>>>>>> Q. >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>&g...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > One last question regarding this please. > > Why aren't we simply changing the register class in AddRegisterOperand instead of building a new COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the number of ASM mov instructions that are