Displaying 20 results from an estimated 30 matches for "srcexists".
2014 Mar 11
2
[PATCH] nv50/ir/gk110: fix some instruction emission
...t subOp)
NEG_(33, 0);
ABS_(31, 0);
-
- // XXX: find saturate
+ SAT_(35, 0);
}
void
@@ -1073,32 +1072,32 @@ CodeEmitterGK110::emitFlow(const Instruction *i)
switch (i->op) {
case OP_BRA:
- code[1] = f->absolute ? 0x00000 : 0x12000000; // XXX
- // if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
- // code[0] |= 0x4000;
+ code[1] = f->absolute ? 0x11000000 : 0x12000000;
+ if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
+ code[0] |= 0x80;
mask = 3;
break;
ca...
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
Something about how we're implementing offsets for TXD is wrong, just
flip to the generic quadop-based implementation in that case.
This is the minimal fix appropriate for backporting.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++-
1 file changed, 2
2014 Mar 11
0
[PATCH] nv50/ir/gk110: fix some instruction emission
...- // XXX: find saturate
> + SAT_(35, 0);
> }
>
> void
> @@ -1073,32 +1072,32 @@ CodeEmitterGK110::emitFlow(const Instruction *i)
>
> switch (i->op) {
> case OP_BRA:
> - code[1] = f->absolute ? 0x00000 : 0x12000000; // XXX
> - // if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
> - // code[0] |= 0x4000;
> + code[1] = f->absolute ? 0x11000000 : 0x12000000;
> + if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
> + code[0] |= 0x80;
> mask...
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
...);
+ insn = insn->getSrc(0)->getUniqueInsnMerged();
if (!insn->bb->reachableBy(texi->bb, term))
return;
@@ -163,7 +163,7 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
case OP_UNION:
/* recurse again */
for (int s = 0; insn->srcExists(s); ++s)
- findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsn(), term,
+ findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsnMerged(), term,
uses);
break;
default:
@@ -200,7 +200,7 @@ NVC0LegalizePostRA::findFirstUses(...
2015 Jan 11
6
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...e)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add << 27;
@@ -1931,11 +1942,6 @@ CodeEmitterNV50::getMinEncodingSize(const Instruction *i) const
// check constraints on short MAD
if (info.srcNr >= 2 && i->srcExists(2)) {
- if (i->saturate || i->src(2).mod)
- return 8;
- if ((i->src(0).mod ^ i->src(1).mod) ||
- (i->src(0).mod | i->src(1).mod).abs())
- return 8;
if (!i->defExists(0) ||
i->def(0).rep()->reg.data.id != i->src(2).re...
2017 Aug 12
3
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...vc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ ImmediateValue imm;
+ // check if we are moving an immediate, propagate it in that case
+ if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) ||
+ !ld->src(0).getImmediate(...
2017 Aug 13
1
[PATCH v2] nvc0/ir: propagate immediates to CALL input MOVs
...vc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ assert(ld->getSrc(0) != NULL);
+ // check if we are moving an immediate, propagate it in that case
+ if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) ||
+ !(ld->src(0...
2015 Jan 11
1
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...gt; code[1] = neg_mul << 26;
>> code[1] |= neg_add << 27;
>> @@ -1931,11 +1942,6 @@ CodeEmitterNV50::getMinEncodingSize(const Instruction *i) const
>>
>> // check constraints on short MAD
>> if (info.srcNr >= 2 && i->srcExists(2)) {
>> - if (i->saturate || i->src(2).mod)
>> - return 8;
>> - if ((i->src(0).mod ^ i->src(1).mod) ||
>> - (i->src(0).mod | i->src(1).mod).abs())
>> - return 8;
>> if (!i->defExists(0) ||
>>...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
...rs/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 22db368..442cedf 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -509,10 +509,13 @@ CodeEmitterGM107::emitBRA()
emitCond5(0x00, CC_TR);
if (!insn->srcExists(0) || insn->src(0).getFile() != FILE_MEMORY_CONST) {
+ int32_t pos = insn->target.bb->binPos;
+ if (writeIssueDelays && !(pos & 0x1f))
+ pos += 8;
if (!insn->absolute)
- emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8));
+...
2014 Jun 03
8
[PATCH v2 0/4] Constant folding of new Instructions
And another try for constant folding of Instructions for nvc0.
Please Review this!
Thanks,
Tobias Klausmann
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant expressions
2015 Jan 23
3
[PATCH 1/2] nv50/ir: Add support for MAD short+IMM notation
...e)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add << 27;
@@ -1931,11 +1942,6 @@ CodeEmitterNV50::getMinEncodingSize(const Instruction *i) const
// check constraints on short MAD
if (info.srcNr >= 2 && i->srcExists(2)) {
- if (i->saturate || i->src(2).mod)
- return 8;
- if ((i->src(0).mod ^ i->src(1).mod) ||
- (i->src(0).mod | i->src(1).mod).abs())
- return 8;
if (!i->defExists(0) ||
i->def(0).rep()->reg.data.id != i->src(2).re...
2014 Jun 03
0
[PATCH v2 4/4] nvc0/ir: Handle OP_POPCNT when folding constant expressions
...unt(a->data.u32 & b->data.u32); break;
+ break;
+ }
default:
return;
}
@@ -966,6 +970,17 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->subOp = 0;
break;
}
+ case OP_POPCNT: {
+ uint32_t res;
+ if (!i->srcExists(1)) {
+ res = util_bitcount(imm0.reg.data.u32);
+ i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), res));
+ i->setSrc(1, NULL);
+ i->op = OP_MOV;
+ i->subOp = 0;
+ }
+ break;
+ }
default:
return;
}
--
1.8.4.5
2015 Jan 11
0
[PATCH 2/3] nv50/ir: For MAD, prefer SDST == SSRC2
...case 0xd0:
@@ -995,6 +996,13 @@ GCRA::doCoalesce(ArrayList& insns, unsigned int mask)
copyCompound(insn->getSrc(0), insn->getDef(0));
}
break;
+ case OP_MAD:
+ if (!(mask & JOIN_MASK_MAD))
+ break;
+ if (insn->srcExists(2) && insn->src(2).getFile() == FILE_GPR &&
+ insn->def(0).getFile() == FILE_GPR)
+ coalesceValues(insn->getDef(0), insn->getSrc(2), false);
+ break;
case OP_TEX:
case OP_TXB:
case OP_TXL:
--
2.1.0
2015 Jan 11
0
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...; 8;
> } else {
> code[1] = neg_mul << 26;
> code[1] |= neg_add << 27;
> @@ -1931,11 +1942,6 @@ CodeEmitterNV50::getMinEncodingSize(const Instruction *i) const
>
> // check constraints on short MAD
> if (info.srcNr >= 2 && i->srcExists(2)) {
> - if (i->saturate || i->src(2).mod)
> - return 8;
> - if ((i->src(0).mod ^ i->src(1).mod) ||
> - (i->src(0).mod | i->src(1).mod).abs())
> - return 8;
> if (!i->defExists(0) ||
> i->def(0).rep()...
2014 Feb 19
0
[PATCH] nv50: enable cube map array texture support
...; i->srcCount() > 4) {
std::vector<Value *> acube, a2d;
int c;
@@ -681,9 +681,10 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
for (c = 0; c < 3; ++c)
i->setSrc(c, a2d[c]);
- i->setSrc(c, NULL);
for (; i->srcExists(c + 1); ++c)
i->setSrc(c, i->getSrc(c + 1));
+ i->setSrc(c, NULL);
+ assert(c <= 4);
i->tex.target = i->tex.target.isShadow() ?
TEX_TARGET_2D_ARRAY_SHADOW : TEX_TARGET_2D_ARRAY;
diff --git a/src/gallium/drivers/nouveau/nv50/nv5...
2014 May 13
1
[PATCH 1/2] nv50/ir: make sure that texprep/texquerylod's args get coalesced
...@ -998,7 +998,9 @@ GCRA::doCoalesce(ArrayList& insns, unsigned int mask)
case OP_TXQ:
case OP_TXD:
case OP_TXG:
+ case OP_TXLQ:
case OP_TEXCSAA:
+ case OP_TEXPREP:
if (!(mask & JOIN_MASK_TEX))
break;
for (c = 0; insn->srcExists(c) && c != insn->predSrc; ++c)
--
1.8.5.5
2017 Aug 12
0
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...eSSA::handleDIV(Instruction *i)
> int builtin;
>
> bld.setPosition(i, false);
> - bld.mkMovToReg(0, i->getSrc(0));
> - bld.mkMovToReg(1, i->getSrc(1));
> +
> + // Generate movs to the input regs for the call we want to generate
> + for (int s = 0; i->srcExists(s); ++s) {
> + Instruction *ld = i->getSrc(s)->getInsn();
> + ImmediateValue imm;
> + // check if we are moving an immediate, propagate it in that case
> + if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) ||
> + !ld...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before.
nothing really changed from the last version, just minor things.
Karol Herbst (5):
nv50/ir: restructure and rename postraconstantfolding pass
nv50/ir: implement mad post ra folding for nvc0+
gk110/ir: add LIMM form of mad
gm107/ir: add LIMM form of mad
nv50/ir: also do PostRaLoadPropagation for FMA
2015 Feb 06
2
[PATCH 1/3] nv50/ir: Add support for MAD 4-byte opcode
...e)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add << 27;
@@ -1931,11 +1934,6 @@ CodeEmitterNV50::getMinEncodingSize(const Instruction *i) const
// check constraints on short MAD
if (info.srcNr >= 2 && i->srcExists(2)) {
- if (i->saturate || i->src(2).mod)
- return 8;
- if ((i->src(0).mod ^ i->src(1).mod) ||
- (i->src(0).mod | i->src(1).mod).abs())
- return 8;
if (!i->defExists(0) ||
i->def(0).rep()->reg.data.id != i->src(2).re...
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
...0.cpp
index 382b02d..44b5ecd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -744,9 +744,15 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
int s = i->srcCount(0xff, true);
if (i->srcExists(s)) // move potential predicate out of the way
i->moveSources(s, 1);
- for (n = 0; n < i->tex.useOffsets; ++n)
+ if (i->op == OP_TXG) {
+ assert(i->tex.useOffsets == 1);
for (c = 0; c < 3; ++c)
- value |= (i->tex.offset[n][c] &am...