Displaying 5 results from an estimated 5 matches for "spus".
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sous
2004 Jun 09
5
"attach" in R corr. to Spus one
Hi,
I am a newbie to R, just trying to switch from
Splus. I am wondering to know if there is any such
command in R as "attach" in Splus which can be used to
attach the full directory.
Also, any idea/referrence about, how to load c
functions in R would be highly appreciated.
Thanks,
Utsav
2008 Feb 13
0
[LLVMdev] OT: Organizing a Supercomputing '08 workshop
...third (I'm a glutton for
punishment.) This year, the focus will be on many/multicore's
programmability gap -- the gap between today's languages and the
multicore/manycore architectures that we're trying to program. A stellar
example is software development on the IBM Cell BE and its SPUs in C/C++.
The workshop will focus on languages, compilers and runtimes that are
targeted for many/multicore architecutes and platforms.
If you know of any good speakers with topics in the workshop's area,
please feel free to contact me.
-scooter
2009 Jan 20
3
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
I just ran across something interesting: DAGCombine inserts a 64-bit
constant as the result of converting a (bitconvert (fabs val)) to a
(and (bitconvert val), i64const).
The problem: i64 constants have to be legalized for the CellSPU
platform. DAGCombine is doing the right thing but it's not doing the
right thing for CellSPU and it's damed difficult to work around this
2011 Jul 16
2
[LLVMdev] [RFC] LegalizeDAG support for targets without subword load/store instructions
...ted to see if there was any interest in something like this
for mainline before writing up something more detailed. Here are a few
supporting details for now:
* Several existing machines don't provide loads and stores for every
power-of-2-sized datatype down to i8. For example, Cell's SPUs only
support 16-byte, 16-byte-aligned memory ops (this restriction is found
for other SIMD processors as well), and some GPUs don't support i8 or
i16 loads/stores.
* Even when short memory operations are possible, sometimes they are
implemented in a very conservative way (e.g., trapping to...
2007 Nov 08
16
HVM domain with write caching going on somewhere to disk
I just about have my PV block device drivers booting, except just before
the login screen appears I get a message that the registry couldn''t be
written out. I''m pretty sure that this is because some data from the
int13 interface provided by the qemu intel ide driver that has been
written, hasn''t actually made it to the block device (lvm volume in my
case).
I''ve