search for: spugencodeemitter

...ned int, unsigned int> > llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) const: > Assertion `i < OperandList.size() && "Invalid flat operand #"' failed. > make: *** > [/work/scottm/llvm/obj/i686-unknown-linux-gnu/lib/Target/IBMCellSPU/ > Debug/SPUGenCodeEmitter.inc.tmp] > Aborted > > Whiskey Tango... Foxtrot? Please file a bug with a reduced test case for it. Evan > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/m...

...n.h:118: std::pair<unsigned int, unsigned int> llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) const: Assertion `i < OperandList.size() && "Invalid flat operand #"' failed. make: *** [/work/scottm/llvm/obj/i686-unknown-linux-gnu/lib/Target/IBMCellSPU/Debug/SPUGenCodeEmitter.inc.tmp] Aborted Whiskey Tango... Foxtrot?

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

...gisterInfo.inc +ARMGenSubtargetInfo.inc +ARMGenDisassemblerTables.inc diff --git a/lib/Target/CellSPU/.gitignore b/lib/Target/CellSPU/.gitignore new file mode 100644 index 0000000..6d3f2d2 --- /dev/null +++ b/lib/Target/CellSPU/.gitignore @@ -0,0 +1,7 @@ +SPUGenAsmWriter.inc +SPUGenCallingConv.inc +SPUGenCodeEmitter.inc +SPUGenDAGISel.inc +SPUGenInstrInfo.inc +SPUGenRegisterInfo.inc +SPUGenSubtargetInfo.inc diff --git a/lib/Target/Hexagon/.gitignore b/lib/Target/Hexagon/.gitignore new file mode 100644 index 0000000..dc7c3b0 --- /dev/null +++ b/lib/Target/Hexagon/.gitignore @@ -0,0 +1,7 @@ +HexagonGenAsmWriter....