Displaying 4 results from an estimated 4 matches for "splitvecop_extract_vector_elt".
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly.
> if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) {
> return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo());
> } else {
> return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Sto...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
..., September 16, 2017 00:38
To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com>
Cc: llvm-dev at lists.llvm.org
Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Hi Elena,
Thanks for your response.
The store is ok but the extending load generates assertion after the store because MemVT is i8 and VT is i1 on following line.
assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && "Should only be an extending load, not truncating!"...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...-----Original Message-----
From: jingu at codeplay.com [mailto:jingu at codeplay.com]
Sent: Friday, September 15, 2017 17:45
To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com
Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Can someone give the comment about it please?
Thanks,
JinGu Kang
On 14/09/17 12:05, jingu at codeplay.com wrote:
> Hi All,
>
> I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I
> have a llvm IR code snippet as following:
>
> llvm IR c...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type is 'v2i1'. If the size of vector element is less than 8bit,
'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT()' function extends the
elements to 8bit and stores them on stack. Finally, the function
generates 'ExtLoad' to load specific element. But if the element's size
is less than 8bit, I think it could be wrong. It looks it needs just
'Load' or "Load and Truncate" t...