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David, Thanks for that - I emailed Karel Gardas. I've got GHC successfully registerised on ARM, and I'm just starting on pushing it upstream. The reason why I'm avoiding the R0-R3 registers is mainly because my qemu-based ARM VM takes days to compile everything, and I was being conservative. The GHC code can call directly out to C, so it would need to save its own R0-R3 when it

...38 #20 0x08f19cde in llvm::PassManager::run (this=0x8047030, M=@0x92b3428) at PassManager.cpp:1682 #21 0x086e8ed1 in main (argc=3, argv=0x8047170) at llc.cpp:341 (gdb) it seems my modified LLVM does not like passing i32 type argument into function @foo. If I comment out line: %6 = load i32* @splim llc does not crash. Also in the llvm::ARMTargetLowering::LowerCall I see a comment about disabling tailcalls just to not break things. I'm quite curious if this is still the case since tailcalls are used in GHC, that's also the reason why I ask about status of LLVM on ARM platform above...

...gt; - ; CHECK-NEXT: movq r1(%rip), %rbx >> - ; CHECK-NEXT: movq r2(%rip), %r14 >> - ; CHECK-NEXT: movq r3(%rip), %rsi >> - ; CHECK-NEXT: movq r4(%rip), %rdi >> - ; CHECK-NEXT: movq r5(%rip), %r8 >> - ; CHECK-NEXT: movq r6(%rip), %r9 >> - ; CHECK-NEXT: movq splim(%rip), %r15 >> - ; CHECK-NEXT: movss f1(%rip), %xmm1 >> - ; CHECK-NEXT: movss f2(%rip), %xmm2 >> - ; CHECK-NEXT: movss f3(%rip), %xmm3 >> - ; CHECK-NEXT: movss f4(%rip), %xmm4 >> + ; CHECK: movsd d2(%rip), %xmm6 >> ; CHECK-NEXT: movsd d1(%rip), %xmm5...