search for: spisd

...JMP, MVT::Other, Custom); + if (Subtarget->is64Bit()) { setOperationAction(ISD::ADDC, MVT::i64, Custom); setOperationAction(ISD::ADDE, MVT::i64, Custom); *************** *** 1808,1835 **** const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((SPISD::NodeType)Opcode) { ! case SPISD::FIRST_NUMBER: break; ! case SPISD::CMPICC: return "SPISD::CMPICC"; ! case SPISD::CMPFCC: return "SPISD::CMPFCC"; ! case SPISD::BRICC: return "SPISD::BRICC"; ! case SPISD::BRXCC: return "SPISD::BRXCC&quo...

...licit delta added to their enum value. Is this documented anywhere that getTargetNode is the preferred method to use in a Custom Lowering function? Even the other backends use getNode in their lowering functions with custom opcodes. This is from SparcISelLowering.cpp CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); Opc = SPISD::BRFCC; } return DAG.getNode(Opc, MVT::Other, Chain, Dest, DAG.getConstant(SPCC, MVT::i32), CompareFlag); Micah -------------- next part -------------- An HTML atta...

...num value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering functions with custom opcodes. > This is from SparcISelLowering.cpp > CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); > if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); > Opc = SPISD::BRFCC; > } > return DAG.getNode(Opc, MVT::Other, Chain, Dest, > DAG.getConstant(SPCC, MVT::i32), CompareFlag); Actually, I'm wrong, sorry about that. I...

hi Tim,guys, it was regarding splitting 16-bit ADDC to two 8-bit ADDC+ADDE. the 8-bit ADDE instruction is defined as: let Constraints="$dst=$op0",mayStore=1, hasSideEffects=0,neverHasSideEffects=1 in def ADDErm: myInstr <0x0, (outs Intregs:$dst) (ins Intregs:$op0,MEMi:$op1), "", [set IntRegs:$dest (adde IntRegs:$op0, (load ADDRi:$op1))] > very unlucky, this

...1..." instruction. However, the backend should work as usual for any other function name. >> >> Now I figured that there are two ways to do this : >> 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. >> >> 2) No modifications to the Lowering phase. However, the pattern corresponding to the "sethi" instruction must be modif...

...gt;> the backend should work as usual for any other function name. >>> >>> Now I figured that there are two ways to do this : >>> 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a >>> special opcode that I have introduced into SPISD namespace) whenever it >>> finds a "call @p0" in the LowerCall function. This node should have an entry >>> in the "SparcInstrInfo.td" file. >>> >>> 2) No modifications to the Lowering phase. However, the pattern >>> corresponding to...

...0x4976c20, 0x49730d0<Mem:LD1[@a](align=2)> Result DAG: SelectionDAG has 21 nodes: 0x49606f0: ch = EntryToken [ORD=1] [ID=0] 0x4972cd0: i8 = undef [ORD=1] [ID=2] 0x49735d0: i8 = Constant<1> [ID=3] 0x4977920: i8 = TargetGlobalAddress<i16* @b> 0 [ID=4] 0x4972fd0: i8 = SPISD::GLOBAL_TRANSFER 0x4977920 [ID=6] 0x49606f0: <multiple use> 0x4972fd0: <multiple use> 0x4972cd0: <multiple use> 0x4976c20: i8,ch = load 0x49606f0, 0x4972fd0, 0x4972cd0<LD1[@b](align=2)> [ID=8] 0x49606f0: <multiple use> 0x4972fd0: <multiple...

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being

...T a "call p0, call p1..." instruction. However, the backend should work as usual for any other function name. Now I figured that there are two ways to do this : 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. 2) No modifications to the Lowering phase. However, the pattern corresponding to the "sethi" instruction must be modified/new pattern a...

When LLVM does a comparison of two vectors, in this case with 16 elements, the returned type of setcc is v16i1. The architecture I'm targeting allows storing the result of a vector comparison as a bit mask in a scalar register, but I'm having trouble converting the result of setcc into a value that is usable there. For example, if I try to AND together masks that are the results of two

...l p0, call p1..." instruction. However, the backend should work as usual for any other function name. > > Now I figured that there are two ways to do this : > 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. > > 2) No modifications to the Lowering phase. However, the pattern corresponding to the "sethi" instruction must be modified/new...

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue

Hello, Im (trying) to write a backend for a simple 32bit processor architecture, with a single instruction format having no condition code registers. www.docm.mmu.ac.uk/STAFF/A.Nisbet/Sabre.pdf is the short 15 page document describing the architecture of Sabre. It is a Celoxica developed research/teaching processor, pages 5-8 contain relevant information for targetting it from a new compiler