search for: spiller

Can someone explain the theory behind the spillers in VirtRegMap.cpp? It seems as though the spillers do triple duty: - Insert load/store operations and/or fold instructions as necessary to carry out spills - Rewrite the spilled virtual registers to use machine registers (mapping given by the caller in the VRM). - Rewrite machine code to...

Hi, Sorry for the delay. I was trying to wrap my head around some live interval analysis code and have forgotten about emails. :-) On Aug 6, 2007, at 9:20 AM, David Greene wrote: > Can someone explain the theory behind the spillers in VirtRegMap.cpp? > > It seems as though the spillers do triple duty: > > - Insert load/store operations and/or fold instructions as > necessary to carry > out spills Actually folding decision was made during allocation. When the allocator decides to spill, it asks live i...

...In my implementation of optimistic register coloring I > precolor spill intervals at the beginning of each iteration and thus don't > have to spill their neghbours specifically. It was done automatically by > Select phase of algorithm. So how did you get around the requirement of the spillers that intervals be mapped to physical registers? Or did you not use the provided spillers? That may be what I end up doing. Loads and stores don't absolutely have to be inserted into the actual instruction text on each iteration, though it is nice for debugging purposes. > As Fernando has...

Hi, Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? Thanks, -- Silvio Ricardo Cordeiro -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100815/66d2d2a7/attachment.html>

Spiller::Spill( LiveInterval *li, SmallVectorImpl<LiveInterval*> &newIntervals, const SmallVectorImpl<LiveInterval*> &spillIs ); has two reference vectors which contain a small list of Live Intervals. What is the register allocator...

...ave. Bill's > implementation has a flavor of it. > >> Unfortunately, it seems that current implementation doesn't support such >> "clever" spilling. > > True. People have talked about adding it ever since I started getting > involved. To be clear, the spiller interface does support (or could with very straight-forward extension) splitting, it just requires you to give the split ranges new intervals and a new vreg. -Chris -- http://nondot.org/sabre/ http://llvm.org/

Jeff Kunkel <jdkunk3 at gmail.com> writes: > Spiller::Spill( LiveInterval *li, >                           SmallVectorImpl<LiveInterval*> &newIntervals, >                           const SmallVectorImpl<LiveInterval*> &spillIs ); > > has two reference vectors which contain a small list of Live > Intervals. What is t...

...oloring I precolor spill intervals at the beginning of each iteration and thus don't have to spill their neghbours specifically. It was done automatically by Select phase of algorithm. As Fernando has mentioned while I was writing this after the last iteration of your algorithm before you call Spiller::runOnMachineFunction method every interval in VirtRegMap must be mapped to a physical register, both spill and others. Hope that helps. Anton. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070806/b5db574...

...icardo Cordeiro wrote: > Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? RALinearScan asks the Spiller to spill a virtual register. The StandardSpiller passes the request to LiveIntervals::addIntervalsForSpills. Here, the spill and restore points are added to the VirtRegMap. No spill code has been inserte...

...mistic register coloring I > > precolor spill intervals at the beginning of each iteration and thus > don't > > have to spill their neghbours specifically. It was done automatically by > > Select phase of algorithm. > > So how did you get around the requirement of the spillers that intervals > be mapped to physical registers? Or did you not use the provided > spillers? > That may be what I end up doing. Loads and stores don't absolutely have > to be > inserted into the actual instruction text on each iteration, though it is > nice > for debugg...

Hi all, I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence. For example: phys_reg = MI1 vreg1 vreg 2 = MI2 phys_reg Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2? I am using greedy register allocator and inline spiller. -- Regards, Dongrui -------------- next part --------...

...en using a debugger for my register allocator. The debugger happened to be very useful at catching register assignment errors. I've put the debugger on-line, if anyone who is working with register allocation wants to use. The debugger itself has nothing to do with LLVM, but I've coded a spiller that prints the code in a format that the debugger can read. The page is: http://compilers.cs.ucla.edu/fernando/projects/debugger/ all the best, Fernando

...gt; > > Is there a way for me to collect statistics about the number of > loads/stores added by the "linearscan" register allocator (just like can be > done with the "local" allocator)? I still haven't grokked very well the > interaction between RALinScan and Spiller... Should I add those two > statistics to the spiller's class? > > RALinearScan asks the Spiller to spill a virtual register. The > StandardSpiller passes the request to LiveIntervals::addIntervalsForSpills. > Here, the spill and restore points are added to the VirtRegMap. No spi...

...E may be the only choice. Because at least for this case I am looking at, what your patch did is created more relatively complex long live range, rematerialization is not smart enough to undo your change or at least without a lot of work, coalescing only create even longer live range not shorter, Spiller can't help since it's the Spiller created Spill/Reloads due to high register pressure, Splitting can shorten the live ranges, but I don't think it can handle your case without a lot of work. Suggestions are welcome. -----Original Message----- From: Daniel Berlin [mailto:dberlin at dbe...

On Wed, Jul 15, 2015 at 1:10 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > IMHO, This doesn't make a lot of sense to turn off this part on it's own. > I would just use the enable-pre flag to turn off scalar PRE, as it > will cause the same issue in other cases as well. > Is there some reason you aren't just doing that? > I suspect if this is a performance

...gt; -----Original Message----- > From: Lawrence [mailto:lawrence at codeaurora.org] > Sent: Wednesday, July 15, 2015 9:36 PM > To: 'Daniel Berlin' > Cc: 'LLVM Developers Mailing List' > Subject: RE: Register pressure mechanism in PRE or Smarter rematerialization/split/spiller/coalescing ? > > Hi, Daniel: > > Thanks, I tried that patch you provided, it is better than just disabling your previous patch, it has more improvements than degradations. > > Do you want to post that patch or you want me to do that? > > Regards > > Lawrence Hu > &g...

Seems to be a bit of new warnings recently: llvm/llvm/lib/CodeGen/Spiller.cpp: In function 'void UpdateKills(llvm::MachineInstr&, llvm::BitVector&, std::vector<llvm::MachineOperand*, std::allocator<llvm::MachineOperand*> >&, const llvm::TargetRegisterInfo*)': llvm/llvm/lib/CodeGen/Spiller.cpp:221: warning: unused variable 'TID&...

> > FYI, in my implementation I just marked the intervals introduced by > spills as being special so that they would not be chosen to be spilled > again. Then they just get colored like every other interval. But they can be uncolored like every other interval then, right? When your algorithm finds out during one iteration that it should spill some interval it checks whether this

...llocator. The > debugger > happened to be very useful at catching register assignment errors. > I've > put the debugger on-line, if anyone who is working with register > allocation wants to use. The debugger itself has nothing to do with > LLVM, > but I've coded a spiller that prints the code in a format that the > debugger can read. The page is: > > http://compilers.cs.ucla.edu/fernando/projects/debugger/ Hi Fernando, This looks quite useful. Do you think you can incorporate the code output the debugging info in smira to tot? Also, it seems to make mo...

I'm not sure about one thing: you assign stack slot to each new register you replace the spilled one with. And then you need to allocate physical registers to them. Is it possible to assign physical register to the virtual one which has a stack slot already? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > > So what addIntervalsToSpills