Displaying 3 results from an estimated 3 matches for "spillalign".
2009 Apr 28
1
[LLVMdev] Register class intersection
...Regs (subset means improper subset)
and A.SpillSize == B.SpillSize
Since the spill sizes differ, FR64 and VR128 have no sub/super class
relation.
I propose that we change the definition to:
A is a subclass of B iff A != B
and A.Regs is a subset of B.Regs
and A.SpillSize >= B.SpillSize
and A.SpillAlignment is divided by B.SpillAlignment
This would introduce two new subclass chains:
RFP80 subclass of RFP64 subclass of RFP32
VR128 subclass of FR64
Define intersection as described above:
intersection(A, B) = max { X | X subclass-eq A, X subclass-eq B }
The coalescer can then use NewRC = interse...
2016 Sep 24
2
RFC: Implement variable-sized register classes
...it works under the hood to the average backend
> writer.
I agree with the complexity, but I would hope that more documentation,
examples and explanations would clarify it.
> What if RegisterClass contained a `list<RCInfo>`. Each RCInfo contains
> RegTypes, RegSize, SpillSize, and SpillAlignment as well as a
> Predicate the determines whether this individual RCInfo is the one
> that should apply. To my taste this seems easier to understand than
> the {Int,ValueType,ValueTypeList}Select mechanism.
The "select" mechanism was intended to be extendable to be able to
se...
2016 Sep 20
7
RFC: Implement variable-sized register classes
...ke
precedence over the existing members RegTypes/Size/Alignment.
class RegisterClass {
...
ValueTypeListSelect VarRegTypes; // The names of these members
IntSelect VarRegSize; // could likely be improved...
IntSelect VarSpillSize; //
IntSelect VarSpillAlignment //
}
To fully implement the AddReg instruction, the target would then define
the register class:
class MyRegisterClass : RegisterClass<...> {
let VarRegTypes = ValueTypeListSelect<[Mode64, Mode128],
[[i64, v2i32, v4i16, v8i8], // Mode64...