Displaying 3 results from an estimated 3 matches for "speex_asm_mmx_sse".
2004 Aug 06
0
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...rder 10 filter is hard-coded and patched to work also for order 8 (less
efficiently). Also, I think this should really go into 1.1.x (to become
1.2). I have already found a faster implementation, which is not yet in
CVS BTW.
About your SPEEX_ASM flags, I'm not sure I see the difference between
SPEEX_ASM_MMX_SSE and SPEEX_ASM_MMX_SSE_FP. Also, you're saying that the
current code makes use of SSE2, which I don't think is the case, since I
developed it on a Pentium III, which only supports SSE1. I don't think
SSE2 is important at all, since most of the SSE2 instructions are for
double precision (...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...i?86 based platform by making a special
define. Second, it adds a new ctl value called SPEEX_SET_ASM_FLAG which
takes in an integer. The values are defined as:
#define SPEEX_SET_ASM_FLAG 200
#define SPEEX_ASM_MMX_NONE 0
#define SPEEX_ASM_MMX_BASIC 1
#define SPEEX_ASM_MMX_SSE 2
#define SPEEX_ASM_MMX_SSE_FP 4
The current Speex SSE code requires full SSE2 support which corresponds to
SPEEX_ASM_MMX_SSE_FP. None of the other defines are actively used, but they
are included since they represent different Intel/AMD processors. For
example, an AMD Duran on...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
...oded and patched to work also for order 8 (less
>efficiently). Also, I think this should really go into 1.1.x (to become
>1.2). I have already found a faster implementation, which is not yet in
>CVS BTW.
>
>About your SPEEX_ASM flags, I'm not sure I see the difference between
>SPEEX_ASM_MMX_SSE and SPEEX_ASM_MMX_SSE_FP. Also, you're saying that the
>current code makes use of SSE2, which I don't think is the case, since I
>developed it on a Pentium III, which only supports SSE1. I don't think
>SSE2 is important at all, since most of the SSE2 instructions are for
>do...