search for: sparctargetlow

...::EH_SJLJ_SETJMP, MVT::i32, Custom); + setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); + if (Subtarget->is64Bit()) { setOperationAction(ISD::ADDC, MVT::i64, Custom); setOperationAction(ISD::ADDE, MVT::i64, Custom); *************** *** 1808,1835 **** const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((SPISD::NodeType)Opcode) { ! case SPISD::FIRST_NUMBER: break; ! case SPISD::CMPICC: return "SPISD::CMPICC"; ! case SPISD::CMPFCC: return "SPISD::CMPFCC"; ! case SPISD::BRICC: return "SPISD::BR...

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

...d i64, i64* @x, align 8 store i64 %0, i64* @y, align 8 turned into just "ldd, std" instructions, as it does in GCC, rather than loading and storing the two 32bit halves of the variables separately. To allow that, I tried adding: addRegisterClass(MVT::i64, &SP::IntPairRegClass) to SparcTargetLowering::SparcTargetLowering in 32bit mode. Doing that then makes load/store work. But it causes llvm to try to use i64 operations for *everything*, which of course fails for all other operations, since there's no such instruction pattern for them. Okay, so I then try setting all the operations...

...@y, align 8 >> turned into just "ldd, std" instructions, as it does in GCC, rather than loading and storing the two 32bit halves of the variables separately. >> >> To allow that, I tried adding: >> addRegisterClass(MVT::i64, &SP::IntPairRegClass) >> to SparcTargetLowering::SparcTargetLowering in 32bit mode. >> >> Doing that then makes load/store work. But it causes llvm to try to use i64 operations for *everything*, which of course fails for all other operations, since there's no such instruction pattern for them. >> >> Okay, so I...

...o just "ldd, std" instructions, as it does in GCC, rather than loading and storing the two 32bit halves of the variables separately. >>>> >>>> To allow that, I tried adding: >>>> addRegisterClass(MVT::i64, &SP::IntPairRegClass) >>>> to SparcTargetLowering::SparcTargetLowering in 32bit mode. >>>> >>>> Doing that then makes load/store work. But it causes llvm to try to use i64 operations for *everything*, which of course fails for all other operations, since there's no such instruction pattern for them. >>>&g...

Hello, LLVM devs. I'm compiling the following simple IR: define dso_local i32 @main(i32 %argc, i8** %argv) { entry: %retval = alloca i32, align 4 %argc.addr = alloca i32, align 4 %argv.addr = alloca i8**, align 8 store i32 0, i32* %retval, align 4 store i32 %argc, i32* %argc.addr, align 4 store i8** %argv, i8*** %argv.addr, align 8 ret i32 0 } using `llc -march=sparc

...tExprWithNewAddressSpace 2 llvm::FastISel::lowerCallTo 2 llvm::RISCVTargetLowering::getTgtMemIntrinsic 2 llvm::SparcTargetLowering::LowerCall_32 2 addByteCountSuffix 2 tryToShorten 2 llvm::InstComb...