search for: sparcisellowering

Hi Raghu, > I am working with the "LowerCall" function, and trying to figure out the types of all the "Outs" arguments. Specifically, I want to find out if a particular "Out[i]" argument is a pointer (of any type), or a regular data type. So far, all pointers show up as the "MVT::i32" datatype, which is not helping my cause. Is there a way to distinguish

Hi all, I am working with the "LowerCall" function, and trying to figure out the types of all the "Outs" arguments. Specifically, I want to find out if a particular "Out[i]" argument is a pointer (of any type), or a regular data type. So far, all pointers show up as the "MVT::i32" datatype, which is not helping my cause. Is there a way to distinguish

..."target" nodes are encoded with an implicit delta added to their enum value. Is this documented anywhere that getTargetNode is the preferred method to use in a Custom Lowering function? Even the other backends use getNode in their lowering functions with custom opcodes. This is from SparcISelLowering.cpp CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); Opc = SPISD::BRFCC; } return DAG.getNode(Opc, MVT::Other, Chain, Dest, DAG.getConstant(SPCC, MVT::i32), CompareFlag); Micah --------------...

...the text "EH_SjLj_Setup". You'll find very similar code in the PowerPC backend. If anyone spots any other mistakes or has comments, I'd be glad to know about them at this stage too. Note: I'll comment as best I can how this works within the code when I get it working. Index: SparcISelLowering.cpp =================================================================== *** SparcISelLowering.cpp (revision 267677) --- SparcISelLowering.cpp (working copy) *************** *** 1586,1591 **** --- 1586,1594 ---- setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); setOperationAction(ISD::SE...

..., I want the backend to generate a "sethi %g0,<number>", and NOT a "call p0, call p1..." instruction. However, the backend should work as usual for any other function name. >> >> Now I figured that there are two ways to do this : >> 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. >> >> 2) No modifications to the Lowering...

...ns like p0(), p1()..etc), I want the backend to generate a "sethi %g0, <number>", and NOT a "call p0, call p1..." instruction. However, the backend should work as usual for any other function name. Now I figured that there are two ways to do this : 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. 2) No modifications to the Lowering phase. However, t...

...s are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering functions with custom opcodes. > This is from SparcISelLowering.cpp > CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); > if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); > Opc = SPISD::BRFCC; > } > return DAG.getNode(Opc, MVT::Other, Chain, Dest, > DAG.getConstant(SPCC, MVT::i32), CompareFlag); Actu...

...;>> "sethi %g0,<number>", and NOT a "call p0, call p1..." instruction. However, >>> the backend should work as usual for any other function name. >>> >>> Now I figured that there are two ways to do this : >>> 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a >>> special opcode that I have introduced into SPISD namespace) whenever it >>> finds a "call @p0" in the LowerCall function. This node should have an entry >>> in the "SparcInstrInfo.td" file. >>> &g...

...align 4 store i8* %ap, i8** %ap.addr, align 4 %0 = va_arg i8** %ap.addr, i64 %conv = trunc i64 %0 to i32 store i32 %conv, i32* @foo_arg, align 4 %1 = va_arg i8** %ap.addr, double %2 = load i32, i32* @foo_arg, align 4 ... I had been attempting to make various changes to SparcISelLowering.cpp to try to simulate something similar where the code is output, but I don't feel as though I'm heading in the right direction. I'm still not sure quite where the source of the problem lies. I can provide more details on specifics, but rather than head off into excessive details imme...

...p1()..etc), I want the backend to generate a "sethi %g0, <number>", and NOT a "call p0, call p1..." instruction. However, the backend should work as usual for any other function name. > > Now I figured that there are two ways to do this : > 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. > > 2) No modifications to the Lowering phase. H...

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being

Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the

Hello, Im back trying to finish my backend to a simple RISC cpu SABRE now that most of the tedious process of examining undergraduate students is out of the way. I have managed to describe the registers and the instructions in the architecture and have added support for 32 bit immediates (thanks to Christopher Lamb) as the instruction set only supports 17 bit immediates directly. Could

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue

On 2008-09-29 07:46, Keun Soo Yim wrote: > Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly > > > > Code: > > register struct thread_info

Hi all, There's been a recent bootstrap failure that might be covered up because of another failure. I just wanted to point this out so that people can take a look: -bw Here's the failure from our buildbot: Assertion failed: (DestReg == VirtReg && "Unknown load situation!"), function RewriteMBB, file /Volumes/Sandbox/Buildbot/llvm/build.llvm-