search for: sparcinstrinfo

...how LLVM does code generation and I have a couple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra", 0b100111, sra>; Is this correct? When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs inc...

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: 19 September 2014 01:36 > To: Sanjay Patel > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] predicates vs. requirements [TableGen, > X86InstrInfo.td] > > On Thu, Sep 18, 2014 at 03:25:07PM -0600, Sanjay Patel wrote: >

...quot;. > The steps to create intrinsic function is documented in > http://llvm.org/docs/ExtendingLLVM.html#intrinsic. > 2. Create a lowering pass that lowers "functions with particular > type" ( eg. p0, p1) to the intrinsic. > 3. Create a instruction pattern in SparcInstrInfo.td that matches > the intrinsic. > From the arguments to the intrinsic function, encode the > "<number>" and output a "sethi" instruction. > > Thanks, > Venkatraman > > > On Tue, Jan 18, 2011 at 11:18 PM, Raghu Prabhakar<raghu at cs.u...

...gured that there are two ways to do this : 1) Modifying the "SparcISelLowering.cpp" to emit a special SDNode (with a special opcode that I have introduced into SPISD namespace) whenever it finds a "call @p0" in the LowerCall function. This node should have an entry in the "SparcInstrInfo.td" file. 2) No modifications to the Lowering phase. However, the pattern corresponding to the "sethi" instruction must be modified/new pattern added which corresponds to "call p0" kind of selectionDAG nodes. In either case, I am a bit confused about how tblgen's patt...

...    The steps to create intrinsic function is documented in >> http://llvm.org/docs/ExtendingLLVM.html#intrinsic. >>   2. Create a lowering pass that lowers "functions with particular >> type" ( eg. p0, p1) to the intrinsic. >>   3. Create a instruction pattern in SparcInstrInfo.td that matches >> the intrinsic. >>       From the arguments to the intrinsic function,  encode the >> "<number>"  and output a "sethi" instruction. >> >> Thanks, >> Venkatraman >> >> >> On Tue, Jan 18, 2011 at 11:18 P...

...tion and I have a couple of questions. > I am using LLVM 2.6. > > First, > if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? > Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > Is this correct? Yes. > When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and...

...ular type of function names". The steps to create intrinsic function is documented in http://llvm.org/docs/ExtendingLLVM.html#intrinsic. 2. Create a lowering pass that lowers "functions with particular type" ( eg. p0, p1) to the intrinsic. 3. Create a instruction pattern in SparcInstrInfo.td that matches the intrinsic. From the arguments to the intrinsic function, encode the "<number>" and output a "sethi" instruction. Thanks, Venkatraman On Tue, Jan 18, 2011 at 11:18 PM, Raghu Prabhakar <raghu at cs.ucla.edu> wrote: > Hello all, > &g...

...I wonder about this directory and the 162 tests that are in it. Most tests have only this run line: ; RUN: llc < %s And when I look at the log of some tests like: test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll The comment inside is: ; This caused the backend to assert out with: ; SparcInstrInfo.cpp:103: failed assertion `0 && "Unexpected unsigned type”’ I doubt we are effectively testing the Sparc backend unless you run the validation on a Sparc. Since “CodeGen” can’t really be generic (you’ll need a target), I’m not sure what is intended to be in it. I’d like to move most...

...backend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td.  So I uninstall llvm and I try to build it manually as specified in Getting Started with the LLVM System. http://llvm.org/releases/2.7/docs/GettingStarted.html. The building finish with out error (I didn\t include LLVM Test Suite). I use default for all of the options!! But when I use all o...

...ch, since sparc != sparc64. > In LLVM sense "sparc" means "sparc with ILP32 architecture model", > llvm does not support anything 64 bit in sparc world SparcTargetMachine.h file lists SparcV9TargetMachine as 64-bit machine and SparcV8TargetMachine as 32-bit machine. And SparcInstrInfo.td seems to contain some of the V9-only instructions. Are you sure 64-bit sparc isn't supported at all? Yuri

Has anybody used the Pattern class. We all use Pat and ComplexPattern but I can't find any examples of Pattern. I have some instructions that I'm currently treating as pseudos but I'd like to treat them as patterns with several instructions but this does not seem to work, at least I can't get it to work so far. I get an error: Cannot handle instructions with temporaries yet!

You might want to refer to lib/Target/Sparc/SparcInstrInfo.td for examples of both Pat and ComplexPattern. Regards. 2012/9/16 Kotler, Reed <rkotler at mips.com>: > Has anybody used the Pattern class. We all use Pat and ComplexPattern but I > can't find any examples of Pattern. > > I have some instructions that I'm currently trea...

.../pre> I want instruction like this <pre> bne %r1, %r2, .label </pre> </BR> I am referring to sparc code for this implementation (llvm-3.1).</BR></BR> 1. Should I change the SPBranch and BCOND structs in .td file.</BR> 2. Should I change BuildMI constructs in SparcInstrInfo::InsertBranch() function in SparcInstrInfo.cpp</BR> Please help me. I am referring LLVM 3.1.</BR> Vikram -- View this message in context: http://llvm.1065342.n5.nabble.com/subcc-problem-wrt-sparc-tp53138.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...e of questions. I am using LLVM 2.6. > > > > First, > > if I want to change the name of an instruction, all I need to do is to > > modify the XXXInstrInfo.td, right? Using Sparc as an example, if I > > wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would > > write, > > > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > > > Is this correct? > > Yes. IMHO, this is a poor way to do this kind of thing. It eventually leads to confusion where someone things SRA means "sra" and som...

...1, reg_imm, rd Operation: prod[31:0] = rs1[15:0] * reg_imm[15:0] result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0] (Y[7:0] & %asr18[31:0]) = result[39:0] rd = result[31:0] %asr18 can be read and written using the rdasr and wrasr instructions. === I have the following in SparcInstrInfo to define the lowering rules for this instruction, but I feel that this isn't likely to work as I need to somehow tie together the fact that %Y, %ASR18 and %rd are all related to each other in the output. let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in def SMACrr...

...ng testcase, > fast register allocator crashes with "UNREACHABLE executed" error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is this is related to this entry in SparcInstrInfo.td: let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1, Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { def CALL : InstSP<(outs), (ins calltarget:$dst),...

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

...lexPattern are used everywhere. ________________________________________ From: Triple Yang [triple.yang at gmail.com] Sent: Sunday, September 16, 2012 9:55 AM To: Kotler, Reed Cc: LLVM-Dev ‎[llvmdev at cs.uiuc.edu]‎ Subject: Re: [LLVMdev] Pattern class You might want to refer to lib/Target/Sparc/SparcInstrInfo.td for examples of both Pat and ComplexPattern. Regards. 2012/9/16 Kotler, Reed <rkotler at mips.com>: > Has anybody used the Pattern class. We all use Pat and ComplexPattern but I > can't find any examples of Pattern. > > I have some instructions that I'm currently trea...

...ackend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td. So I uninstall llvm and I try to build it manually as specified in Getting Started with the LLVM System. http://llvm.org/releases/2.7/docs/GettingStarted.html. The building finish with out error (I didn\t include LLVM Test Suite ). I use default for all of the options!! But when I use all...

...lectAddr so it doesn't fold the add node but > instead returns two operands: one for the pointer and one for the offset. > You can control the register classes for the two components of the address > using MIOperandInfo so your base pointer can be IClass and the offset > MClass. See SparcInstrInfo.td (and probably others) for examples. > > I'm assuming you meant r1 = *(i0 + m0) rather than r1 = *(i0 += m0)? I > don't know how you'd achieve that latter. > > Steve Montgomery > > On 21 Oct 2014, at 17:15, Johnny Val <johnnydval at gmail.com> wrote: > &g...