search for: sor

...ia.com/open-gpu-doc/DCB/2/DCB-4.x-Specification.html >> >> >> >> You can diff it against the previous version: >> >> >> >> ftp://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html >> >> >> >> to see what changed (sorry for having to diff html files). The biggest >> >> differences are Serial Output Resource (SOR) assignment, and the updated >> >> Communications Control Block layout. >> > Thanks for the heads-up on the update. The SOR assignment changes >> > explain som...

...d DCB spec here: >> >> ftp://download.nvidia.com/open-gpu-doc/DCB/2/DCB-4.x-Specification.html >> >> You can diff it against the previous version: >> >> ftp://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html >> >> to see what changed (sorry for having to diff html files). The biggest >> differences are Serial Output Resource (SOR) assignment, and the updated >> Communications Control Block layout. > Thanks for the heads-up on the update. The SOR assignment changes > explain some things I noticed when bringing up...

...> ftp://download.nvidia.com/open-gpu-doc/DCB/2/DCB-4.x-Specification.html > >> > >> You can diff it against the previous version: > >> > >> ftp://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html > >> > >> to see what changed (sorry for having to diff html files). The biggest > >> differences are Serial Output Resource (SOR) assignment, and the updated > >> Communications Control Block layout. > > Thanks for the heads-up on the update. The SOR assignment changes > > explain some things I notic...

I have one fixed effect, sor, with two levels. I have eight lots and three wafers from each lot. I have included the data below. I would like to fit a mixed model that estimates a covariance parameter for wafer, which is nested in lot, and two covariance parameters for lot, one for each level of sor. The following command...

https://bugs.freedesktop.org/show_bug.cgi?id=89272 Bug ID: 89272 Summary: GM206 does not recognize attached hdmi monitor Product: xorg Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at

Hi Ben, still _assuming_ it's an issue of the card I thought about why it works with the NVIDIA binary driver. And I can image they're just trying to do an identity-mapping first and if that doesn't work (e.g. the particular SOR is already in use by another macro link) they just pick the next suitable one. So the case would be that the NVIDIA binary driver always assignes the only working mapping (SOR-1 <-> macro link D) on a Gainward GTX 1070. Therefore, if this is the case, maybe it is better to change the routin...

On 2018-02-05 02:39, Ben Skeggs wrote: > On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: >> On 5 February 2018 at 11:22, Danilo Krummrich >> <danilokrummrich at dk-develop.de> wrote: >>> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >>> 'G' (outp index 7) causes failures: >>> >>> [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT >>> at 61c880 [ IBUS ] >>> [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 >>> [...

https://bugs.freedesktop.org/show_bug.cgi?id=60680 Priority: medium Bug ID: 60680 Assignee: nouveau at lists.freedesktop.org Summary: HDMI is connected and has mode, TV says "no signal" QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: Linux (All) Reporter:

...> >> https://fedorapeople.org/~jwrdegoede/mmiotrace.log.xz >> >> And a demmio-ed version (with color esc sequences) here: >> >> https://fedorapeople.org/~jwrdegoede/demmio.log.xz >> >> Some pointers where in this can I find the relevant parts (the supervisor >> irq handling) for this problem would be welcome :) > Look for reads from register 0x610024. A value of 0x10 is the start of > supervisor 0 (nv50_disp_intr_unk10), 0x20 for supervisor 1 > (nv50_disp_intr_unk20), 0x40 for supervisor 2 (nv50_disp_intr_unk40). > > The end of su...

With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a...

With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a...

...er, hdr, cnt, len; u16 data; u32 ctrl = 0x00000000; + u32 reg; int i; /* DAC */ - for (i = 0; !(ctrl & (1 << head)) && i < 3; i++) + for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); /* SOR */ @@ -845,19 +846,18 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) if (nv_device(priv)->chipset < 0x90 || nv_device(priv)->chipset == 0x92 || nv_device(priv)->chipset == 0xa0) { - for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)...

...homas Zimmermann <tzimmermann at suse.de> --- drivers/gpu/drm/tegra/drm.h | 2 -- drivers/gpu/drm/tegra/dsi.c | 10 +++------- drivers/gpu/drm/tegra/hdmi.c | 9 +++------ drivers/gpu/drm/tegra/output.c | 6 +----- drivers/gpu/drm/tegra/rgb.c | 8 ++------ drivers/gpu/drm/tegra/sor.c | 8 ++------ 6 files changed, 11 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index ed99b67deb29..804869799305 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -152,8 +152,6 @@ enum drm_connector_status t...

...>> >> On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: >>> >>> On 5 February 2018 at 11:22, Danilo Krummrich >>> <danilokrummrich at dk-develop.de> wrote: >>>> >>>> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >>>> 'G' (outp index 7) causes failures: >>>> >>>> [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at >>>> 61c880 [ IBUS ] >>>> [ 6.724888] nouveau 0000:01:00.0: disp: intr24 800000...

On 5 February 2018 at 11:22, Danilo Krummrich <danilokrummrich at dk-develop.de> wrote: > On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link > 'G' (outp index 7) causes failures: > > [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] > [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 > [ 8.716668] nouveau 0000:01:00.0: DRM: base-0: timeout...

Dear r-help, I have a matrix, suppose, 10x10, and I need the matrix 5x5, having in each cell a mean value of the cells from the initial matrix. Please, point me to a function in R, which can help me doing that. Digging the documentation and mail archives didn't give me a result. Thank you. --- Best regards, Vladimir mailto:wl at eimb.ru

On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link 'G' (outp index 7) causes failures: [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 [ 8.716668] nouveau 0000:01:00.0: DRM: base-0: timeout [ 10.716679] nouveau...

On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: > On 5 February 2018 at 11:22, Danilo Krummrich > <danilokrummrich at dk-develop.de> wrote: >> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >> 'G' (outp index 7) causes failures: >> >> [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] >> [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 >> [ 8.716668] nouveau 0000:01:00.0:...

...awing the frambuffer switching to vt7 does not change the screen expected: - KMS console works - X draws a blank white screen on LVDS-1 (in vt7) - xrandr can enable DP-1 [notes] kernel reports several: [drm] nouveau 0000:01:00.0: 0xD404: Init table command not found: 0x3A errors. what is SOR? [drm] nouveau 0000:01:00.0: plugged DisplayPort-1 [drm] nouveau 0000:01:00.0: 0xD076: Init table command not found: 0x3A [drm] nouveau 0000:01:00.0: SOR-1: link training failed [drm] nouveau 0000:01:00.0: SOR-1: link training failed [drm] nouveau 0000:01:00.0: SOR-1: link training failed [drm] nou...

small update to my last version I sent out. Patches 3-6 are optional and should only improve detecting the max clocks for HDMI and DP, but they didn't underwent big testing and I am a bit concerned, that it might break detecting the DP limits on some boards. Karol Herbst (6): kms/nv50: move nv50_mstm out of the dp union in nouveau_encoder kms/nv50: reject interlaced modes if the hardware