Displaying 4 results from an estimated 4 matches for "someinstance".
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2006 Dec 28
2
STI, controllers and views
Hello,
I have set up that uses single table inheritance. I have a number of
model subclasses following the example in AWDWR that uses Manager <
Employee < Person.
First question. Do I need to create controller classes for each? I
don''t think I do because a single controller should be able to shunt the
data between the models and the views.
Second question. Say I have a view
2009 Feb 24
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Duncan:
I'm still stymied how this whole thread ended up about shuffle vector nodes,
when the original problem was my build vector patch. I'm still working on
backing the build vector patch out (it isn't clean with all of the
intervening commits and I have pressing management tasks which command my
attention.)
-scooter
On Tue, Feb 24, 2009 at 12:28 AM, Duncan Sands <baldrick at
2009 Feb 24
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
> 3. Introduce a new ShuffleVectorSDNode that only has two SDValue
> operands (the two input vectors), but that also contains an array of
> ints in the node (not as operands).
...
> The important part of #3 is that we really want an array of ints
> (using -1 for undef) for the shuffle mask, not "operands". This
> eliminates the nastiness we have now were we
2020 Feb 24
5
[RFC] DebugInfo: A different way of specifying variable locations post-isel
Hi debuginfo cabal,
tl;dr: I'd like to know what people think about an alternative to
DBG_VALUE instructions describing variable locations in registers,
virtual or real. Before instruction selection in LLVM-IR we identify
the _values_ of variables [0] by the instruction that computes the
value; I believe we should be able to do the same post-isel, and it
would avoid having to analyse register