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Hi Paul, On 02/24/2013 08:54 PM, Paul Sokolovsky wrote: > Hello, > > On Sun, 24 Feb 2013 19:15:27 +0100 > Sebastian Dreßler <dressler at zib.de> wrote: > > [] > >> For a project involving a tree data structure, we created a graph for >> representing IR for further analysis. I attached an excerpt of such a >> graph to give you an idea. If it helps,

Hello, On Sun, 24 Feb 2013 19:15:27 +0100 Sebastian Dreßler <dressler at zib.de> wrote: [] > For a project involving a tree data structure, we created a graph for > representing IR for further analysis. I attached an excerpt of such a > graph to give you an idea. If it helps, we will see how to proceed ;) Well, after grepping LLVM source for apparent lack of it and googling for

Hi, I have read an email from the mail list. And I have a question about loop rotation. What is it if it is the case below. -------------------------------------------------------------------------- loop: A br X B br Y C br loop, Z ------------------------------------------------- Thanks! Jerry [LLVMdev] Loop rotation and loop inversion in LLVM? Andrew Trickatrick at apple.com Mon May 20

On Mon, May 13, 2013 at 5:31 PM, Paul Sokolovsky <pmiscml at gmail.com> wrote: > Hello, > > I only recently started to look at LLVM assembly generated by Clang, > and one of the first thing I saw was like: > > define i32 @foo(i32 %a, i32 %b) nounwind { > %1 = tail call i32 @bar(i32 %a) nounwind > %2 = icmp eq i32 %1, 0 > br i1 %2, label %5, label %3 >

Hello, I only recently started to look at LLVM assembly generated by Clang, and one of the first thing I saw was like: define i32 @foo(i32 %a, i32 %b) nounwind { %1 = tail call i32 @bar(i32 %a) nounwind %2 = icmp eq i32 %1, 0 br i1 %2, label %5, label %3 ; <label>:3 ; preds = %0 %4 = add nsw i32 %b, %a br label %7 I wondered what ";

Hi, On 02/24/2013 06:39 PM, Paul Sokolovsky wrote: > Hello, > > LLVM provides several ways to visual IR structure straight in its core - > Function::viewCFG() to render control flow graph, then -view-* options > to llc to render various stages of transforming to machine code. > However, I wasn't able to find a way to render complete DAG > visualization of normal IR -

Hello, LLVM provides several ways to visual IR structure straight in its core - Function::viewCFG() to render control flow graph, then -view-* options to llc to render various stages of transforming to machine code. However, I wasn't able to find a way to render complete DAG visualization of normal IR - which besides CFG would also show dataflow (and other flows, if any). What people use to

FYI for people who may be interested in using LLVM with 8-bit CPUs. Begin forwarded message: Date: Sat, 11 May 2013 15:29:12 +0300 From: Paul Sokolovsky To: sdcc-devel at lists.sourceforge.net Subject: Accepting iCode as input to SDCC Hello, I'm interested to make SDCC accept iCode (its own intermediate representation) as an input format. The motivation being taking intermediate format

Hello, On Fri, 22 Feb 2013 16:50:39 +0400 Anton Korobeynikov <anton at korobeynikov.info> wrote: > Hello > > > I'm trying to understand how fitting source integer type width into > > target machine register width happens. My reading on LLVM > > codegeneration topics (few megabytes) so far didn't have this topic > > mentioned explicitly. > This is

Hello, I'd be interested in knowing which pass performs loop inversion, i.e. transforms while loop into do/while wrapped with if. So, it's pretty easy to understand concept, http://en.wikipedia.org/wiki/Loop_inversion provides description of how its done and motivation, googling gives several relevant references, i.e. it's pretty settled term. I also see this transform to be actually

Hello, I'm trying to understand how fitting source integer type width into target machine register width happens. My reading on LLVM codegeneration topics (few megabytes) so far didn't have this topic mentioned explicitly. As an example, how %1 = add nsw i32 %b, %a gets compiled into msp430 (16bit CPU) assembly as: add.w r13, r15 addc.w r12, r14 Using -print-before-all

flight 18805 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18805/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-rhel6hvm-amd 7 redhat-install fail REGR. vs. 12557 test-amd64-i386-pair 17 guest-migrate/src_host/dst_host fail REGR. vs. 12557 Regressions which are regarded as

flight 18844 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18844/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: build-i386 4 xen-build fail REGR. vs. 12557 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-pcipt-intel 9 guest-start fail

flight 17901 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/17901/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-qemuu-rhel6hvm-intel 4 xen-install fail REGR. vs. 12557 test-amd64-i386-pv 4 xen-install fail REGR. vs. 12557 test-amd64-amd64-pv 4

flight 17916 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/17916/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-amd64-pv 4 xen-install fail REGR. vs. 12557 test-amd64-amd64-xl 4 xen-install fail REGR. vs. 12557 test-amd64-amd64-xl-win7-amd64 4

flight 18150 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18150/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-rhel6hvm-amd 7 redhat-install fail REGR. vs. 12557 test-amd64-i386-pair 17 guest-migrate/src_host/dst_host fail REGR. vs. 12557 Regressions which are regarded as

flight 18181 linux-linus real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18181/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-rhel6hvm-amd 7 redhat-install fail REGR. vs. 12557 test-amd64-i386-pair 17 guest-migrate/src_host/dst_host fail REGR. vs. 12557 Regressions which are regarded as

Hello, (Sorry if this is a FAQ, I did my googling homework and found nothing though.) Is it possible to have a machine backend as a plugin in LLVM? My current reading suggests that no, as some static changes to core are still required to enumerrate triples, backend types, etc. That info is apparently for previous versions of LLVM, and I wonder what is a current state. So, are machine plugins

Hello, I'm interested in LLVM as an opportunity to support C++ programming for legacy MCUs (8051, PIC1x, etc.). Recently, I tried to use C Backend as means to achieve this. As C Backend was removed in recent LLVM versions, I started with LLVM 3.0 which was last version to include it. For starters, I played with MSP430 target, which is supported by LLVM, so allows roundtrip experiments