Displaying 1 result from an estimated 1 matches for "soc_proposal".
2006 May 31
0
Theora Decoding on FPGA
...is Felipe and I sent a proposal to the Google Summer of Code
that the goal is to get a FPGA embeded system decoding Theora Streams
in real-time.
It was accepted and the mentor is the Ralph Giles.
The proposal can be viewd here:
http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt
There is also a presentation with a better division of the hardware modules:
http://svn.xiph.org/trunk/theora-fpga/doc/hard_theora.pdf
Now, I'm working on it, and today I did a simple implementation of the
IDctSlow procedure as a VHDL module.
This module run and decode samples correctly...