Displaying 4 results from an estimated 4 matches for "snax".
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2014 Apr 16
2
[LLVMdev] X86 mmx movq disassembler fail
0x0f 0x6f 0xc8
And
0x0f 0x7f 0xc1
Should both be movq % mm0, % mm1. (AT&T)
However, llvm 3.4 at least does not recognise the second variant as being a
valid instruction.
We are currently compiling up latest src incase it has been fixed. If not,
could someone take a look or recommend how to fix?
Lee
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2013 Mar 20
2
[LLVMdev] Strange spill behaviour
Hi,
While working some more on the backend, I've added callee register saving
and have come across something odd (I assume its because i've not
implemented something), this is with optimisations which makes it even more
odd :
MOV.L [R7+ 12], R1 ; 4-byte Folded Spill
MOV.L [R7+ 8], R2 ; 4-byte Folded Spill
ADD.L R0,R0 + R1
ADD.L
2013 Mar 18
5
[LLVMdev] Hit a snag while attempting to write a backend - any advice?
Hi,
I've been experimenting with writing a backend for LLVM (3.2) (having
already written a frontend http://savourysnax.github.com/EDL), everything
was going reasonably ok ( calls/returns, epilogue, prologue, etc are all
working), up until I tried to place support for conditional branches.
Given this simple program :
int test(int c,int d)
{
if (c)
{
return d;
}
else...
2013 Apr 24
1
[LLVMdev] Backend : What am I missing here
Hi,
While working on adding newlib to my backend I hit the following assert :
Assertion failed: BestRC && "Couldn't find the register class", file
TargetRegisterInfo.cpp, line 112
The following llvm causes this :
define void @specialBreak(i8* %out) nounwind {
entry:
%out.addr = alloca i8*, align 4
store i8* %out, i8** %out.addr, align 4
%0 = load i8** %out.addr,