search for: smsw

Hi all, Does anyone have thoughts on extending v->arch.hvm_vcpu.single_step to support pre-MTF systems, in a way that would mimic the MTF? So far I''m emulating PUSHF/POPF to hide the hypervisor''s trap flag, and eventually I''ll multiplex it down to the guest, but I''m having issues. Right now, I''m enabling X86_EFLAGS_TF in vmx_intr_assist, just like

The lmsw instruction can be used to set CR0_PE, but can never clear it, once set. Currently, as far as I can see, there is no provision to keep lmsw from clearing CR0_PE, either in the vmx code or in x86_emulate code (which is used by SVM to emulate lmsw). This patch fixes this issue. Signed-off-by: Trolle Selander <trolle.selander@eu.citrix.com>

...ed; --------------------------------- ; ; Routine to copy in/out of high memory ; esi = linear source address ; edi = linear target address ; ecx = 32-bit word count ; ; Assumes cs = ds = es ; bcopy: push eax push ebx push edx push ebp test byte [ConfigFlags],CONFIG_RAW jz .anymode smsw ax ; Unprivileged! test al,01h jnz .protmode .realmode: TRACER 'r' ; We're in real mode, do it outselves pushfd ; <- *** push 1 *** push ds ; <- *** push 2 *** push es ; <- *** push 3 *** cli cld --------------------------------- then a little further d...

...is, inline implementations of the native instructions, which are not + rewritten by the hypervisor. Some of these calls are performance critical + during context switch paths, and some are not, but they are all included + for completeness, with the exceptions of the obsoleted LMSW and SMSW + instructions. + + VMI_WRMSR + + VMICALL void VMI_WRMSR(VMI_UINT64 val, VMI_UINT32 reg); + + Write to a model specific register. This functions identically to the + hardware WRMSR instruction. Note that a hypervisor may not implement + the full set of MSRs supported...

...is, inline implementations of the native instructions, which are not + rewritten by the hypervisor. Some of these calls are performance critical + during context switch paths, and some are not, but they are all included + for completeness, with the exceptions of the obsoleted LMSW and SMSW + instructions. + + VMI_WRMSR + + VMICALL void VMI_WRMSR(VMI_UINT64 val, VMI_UINT32 reg); + + Write to a model specific register. This functions identically to the + hardware WRMSR instruction. Note that a hypervisor may not implement + the full set of MSRs supported...

A character device for accessing (in user-space) pages that have been granted by other domains. Signed-off-by: Derek Murray <Derek.Murray@cl.cam.ac.uk> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel