search for: smp_rmb

...ead_barrier_depends(), but SYNC_RMB probably does not suffice. > The reason for this is that smp_read_barrier_depends() must order the > pointer load against any subsequent read or write through a dereference > of that pointer. For example: > > p = READ_ONCE(gp); > smp_rmb(); > r1 = p->a; /* ordered by smp_rmb(). */ > p->b = 42; /* NOT ordered by smp_rmb(), BUG!!! */ > r2 = x; /* ordered by smp_rmb(), but doesn't need to be. */ > > In contrast: > > p = READ_ONCE(gp); > smp_read_barrier_depends();...

...ead_barrier_depends(), but SYNC_RMB probably does not suffice. > The reason for this is that smp_read_barrier_depends() must order the > pointer load against any subsequent read or write through a dereference > of that pointer. For example: > > p = READ_ONCE(gp); > smp_rmb(); > r1 = p->a; /* ordered by smp_rmb(). */ > p->b = 42; /* NOT ordered by smp_rmb(), BUG!!! */ > r2 = x; /* ordered by smp_rmb(), but doesn't need to be. */ > > In contrast: > > p = READ_ONCE(gp); > smp_read_barrier_depends();...

...ry model so that core code doesn't need to worry about the > underlying architecture for synchronisation purposes. It seems you don't listen me. I said multiple times - MIPS implementation of SYNC_RMB/SYNC_WMB/SYNC_MB/SYNC_ACQUIRE/SYNC_RELEASE instructions matches the description of smp_rmb/smp_wmb/smp_mb/sync_acquire/sync_release from Documentation/memory-barriers.txt file. What else do you want from me - RTL or microArch design for that? - Leonid.

...ry model so that core code doesn't need to worry about the > underlying architecture for synchronisation purposes. It seems you don't listen me. I said multiple times - MIPS implementation of SYNC_RMB/SYNC_WMB/SYNC_MB/SYNC_ACQUIRE/SYNC_RELEASE instructions matches the description of smp_rmb/smp_wmb/smp_mb/sync_acquire/sync_release from Documentation/memory-barriers.txt file. What else do you want from me - RTL or microArch design for that? - Leonid.

...e. > > > The reason for this is that smp_read_barrier_depends() must order the > > > pointer load against any subsequent read or write through a dereference > > > of that pointer. For example: > > > > > > p = READ_ONCE(gp); > > > smp_rmb(); > > > r1 = p->a; /* ordered by smp_rmb(). */ > > > p->b = 42; /* NOT ordered by smp_rmb(), BUG!!! */ > > > r2 = x; /* ordered by smp_rmb(), but doesn't need to be. */ > > > > > > In contrast: > > > > > &...

...e. > > > The reason for this is that smp_read_barrier_depends() must order the > > > pointer load against any subsequent read or write through a dereference > > > of that pointer. For example: > > > > > > p = READ_ONCE(gp); > > > smp_rmb(); > > > r1 = p->a; /* ordered by smp_rmb(). */ > > > p->b = 42; /* NOT ordered by smp_rmb(), BUG!!! */ > > > r2 = x; /* ordered by smp_rmb(), but doesn't need to be. */ > > > > > > In contrast: > > > > > &...

...de733e 100644 --- a/arch/powerpc/lib/locks.c +++ b/arch/powerpc/lib/locks.c @@ -30,7 +30,7 @@ void splpar_spin_yield(arch_spinlock_t *lock) yield_count = be32_to_cpu(lppaca_of(holder_cpu).yield_count); if ((yield_count & 1) == 0) return; /* virtual cpu is currently running */ - rmb(); + smp_rmb(); if (lock->slock != lock_value) return; /* something has changed */ plpar_hcall_norets(H_CONFER, @@ -56,7 +56,7 @@ void splpar_rw_yield(arch_rwlock_t *rw) yield_count = be32_to_cpu(lppaca_of(holder_cpu).yield_count); if ((yield_count & 1) == 0) return; /* virtual cpu is cur...

...ipts/checkpatch.pl > index 2b3c228..0245bbe 100755 > --- a/scripts/checkpatch.pl > +++ b/scripts/checkpatch.pl > @@ -5116,7 +5116,14 @@ sub process { > ? } > ? } > ?# check for memory barriers without a comment. > - if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { > + > + my @barriers = ('mb', 'rmb', 'wmb', 'read_barrier_depends'); > + my @smp_barriers = ('smp_store_release', 'smp_load_acquire', 'smp_store_mb'); > + > + @smp_barriers = (@smp_barr...

...ipts/checkpatch.pl > index 2b3c228..0245bbe 100755 > --- a/scripts/checkpatch.pl > +++ b/scripts/checkpatch.pl > @@ -5116,7 +5116,14 @@ sub process { > ? } > ? } > ?# check for memory barriers without a comment. > - if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { > + > + my @barriers = ('mb', 'rmb', 'wmb', 'read_barrier_depends'); > + my @smp_barriers = ('smp_store_release', 'smp_load_acquire', 'smp_store_mb'); > + > + @smp_barriers = (@smp_barr...

On Thu, Dec 31, 2015 at 09:08:38PM +0200, Michael S. Tsirkin wrote: > This defines __smp_xxx barriers for s390, > for use by virtualization. > > Some smp_xxx barriers are removed as they are > defined correctly by asm-generic/barriers.h > > Note: smp_mb, smp_rmb and smp_wmb are defined as full barriers > unconditionally on this architecture. > > Signed-off-by: Michael S. Tsirkin <mst at redhat.com> > Acked-by: Arnd Bergmann <arnd at arndb.de> > --- > arch/s390/include/asm/barrier.h | 15 +++++++++------ > 1 file changed,...

On Thu, Dec 31, 2015 at 09:08:38PM +0200, Michael S. Tsirkin wrote: > This defines __smp_xxx barriers for s390, > for use by virtualization. > > Some smp_xxx barriers are removed as they are > defined correctly by asm-generic/barriers.h > > Note: smp_mb, smp_rmb and smp_wmb are defined as full barriers > unconditionally on this architecture. > > Signed-off-by: Michael S. Tsirkin <mst at redhat.com> > Acked-by: Arnd Bergmann <arnd at arndb.de> > --- > arch/s390/include/asm/barrier.h | 15 +++++++++------ > 1 file changed,...

Andy Lutomirski <luto at amacapital.net> writes: > On Tue, Feb 14, 2017 at 7:50 AM, Vitaly Kuznetsov <vkuznets at redhat.com> wrote: >> Thomas Gleixner <tglx at linutronix.de> writes: >> >>> On Tue, 14 Feb 2017, Vitaly Kuznetsov wrote: >>> >>>> Hi, >>>> >>>> while we're still waiting for a definitive ACK

Andy Lutomirski <luto at amacapital.net> writes: > On Tue, Feb 14, 2017 at 7:50 AM, Vitaly Kuznetsov <vkuznets at redhat.com> wrote: >> Thomas Gleixner <tglx at linutronix.de> writes: >> >>> On Tue, 14 Feb 2017, Vitaly Kuznetsov wrote: >>> >>>> Hi, >>>> >>>> while we're still waiting for a definitive ACK

...need > >to worry about the underlying architecture for synchronisation > >purposes. > > It seems you don't listen me. I said multiple times - MIPS > implementation of > SYNC_RMB/SYNC_WMB/SYNC_MB/SYNC_ACQUIRE/SYNC_RELEASE instructions > matches the description of > smp_rmb/smp_wmb/smp_mb/sync_acquire/sync_release from > Documentation/memory-barriers.txt file. > > What else do you want from me - RTL or microArch design for that? I suspect that it is more likely that we are talking past each other. This stuff is subtle and although we have better ways of tal...

On 01/14/2016 12:48 PM, Paul E. McKenney wrote: > > So SYNC_RMB is intended to implement smp_rmb(), correct? Yes. > > You could use SYNC_ACQUIRE() to implement read_barrier_depends() and > smp_read_barrier_depends(), but SYNC_RMB probably does not suffice. If smp_read_barrier_depends() is used to separate not only two reads but read pointer and WRITE basing on that pointer (example...

On 01/14/2016 12:48 PM, Paul E. McKenney wrote: > > So SYNC_RMB is intended to implement smp_rmb(), correct? Yes. > > You could use SYNC_ACQUIRE() to implement read_barrier_depends() and > smp_read_barrier_depends(), but SYNC_RMB probably does not suffice. If smp_read_barrier_depends() is used to separate not only two reads but read pointer and WRITE basing on that pointer (example...

...;> As far as I understand this helps with situations you described above as >> guest will notice either invalid value of 0 or seq change. In case the >> implementation in real Hyper-V is the same we're safe with compile >> barriers only. > > On x86 that's correct. smp_rmb() resolves to barrier(), but you certainly > need the smp_wmb() on the writer side. > > Now looking at the above your reader side code is bogus: > > + while (1) { > + sequence = tsc_pg->tsc_sequence; > + if (!sequence) > +...

...;> As far as I understand this helps with situations you described above as >> guest will notice either invalid value of 0 or seq change. In case the >> implementation in real Hyper-V is the same we're safe with compile >> barriers only. > > On x86 that's correct. smp_rmb() resolves to barrier(), but you certainly > need the smp_wmb() on the writer side. > > Now looking at the above your reader side code is bogus: > > + while (1) { > + sequence = tsc_pg->tsc_sequence; > + if (!sequence) > +...

...C_RMB probably does not suffice. > > The reason for this is that smp_read_barrier_depends() must order the > > pointer load against any subsequent read or write through a dereference > > of that pointer. For example: > > > > p = READ_ONCE(gp); > > smp_rmb(); > > r1 = p->a; /* ordered by smp_rmb(). */ > > p->b = 42; /* NOT ordered by smp_rmb(), BUG!!! */ > > r2 = x; /* ordered by smp_rmb(), but doesn't need to be. */ > > > > In contrast: > > > > p = READ_ONCE(gp); >...

...ws and becomes 0 :) > As far as I understand this helps with situations you described above as > guest will notice either invalid value of 0 or seq change. In case the > implementation in real Hyper-V is the same we're safe with compile > barriers only. On x86 that's correct. smp_rmb() resolves to barrier(), but you certainly need the smp_wmb() on the writer side. Now looking at the above your reader side code is bogus: + while (1) { + sequence = tsc_pg->tsc_sequence; + if (!sequence) + break; Why would you break out...