Displaying 9 results from an estimated 9 matches for "smp_mb__after_release_acquire".
2016 Jan 15
1
[v3,11/41] mips: reuse asm-generic/barrier.h
...cal transitivity and
> gives an example.
>
> Reported-by: Peter Zijlstra <peterz at infradead.org>
> Reported-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
I think it fails to mention smp_mb__after_release_acquire(), although I
suspect we didn't actually introduce the primitive yet, which raises the
point, do we want to?
2016 Jan 15
1
[v3,11/41] mips: reuse asm-generic/barrier.h
...cal transitivity and
> gives an example.
>
> Reported-by: Peter Zijlstra <peterz at infradead.org>
> Reported-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
I think it fails to mention smp_mb__after_release_acquire(), although I
suspect we didn't actually introduce the primitive yet, which raises the
point, do we want to?
2016 Jan 26
0
[v3,11/41] mips: reuse asm-generic/barrier.h
...&& r4 == 0
>
> I think you should be completely explicit and include r5 == 1 here, too.
Good point -- I added this as an additional outcome:
r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
> Also -- where would you add the smp_mb__after_release_acquire to fix
> (i.e. forbid) this? Immediately after cpu1()'s read of y?
That sounds plausible, but we would first have to agree on exactly
what smp_mb__after_release_acquire() did. ;-)
> > +Although cpu0(), cpu1(), and cpu2() will see their respective reads and
> > +writes in order...
2016 Jan 25
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...> +CPUs and does not apply to cpu3(). Therefore, the following outcome
> +is possible:
> +
> + r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
I think you should be completely explicit and include r5 == 1 here, too.
Also -- where would you add the smp_mb__after_release_acquire to fix
(i.e. forbid) this? Immediately after cpu1()'s read of y?
> +Although cpu0(), cpu1(), and cpu2() will see their respective reads and
> +writes in order, CPUs not involved in the release-acquire chain might
> +well disagree on the order. This disagreement stems from the fact th...
2016 Jan 25
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...> +CPUs and does not apply to cpu3(). Therefore, the following outcome
> +is possible:
> +
> + r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
I think you should be completely explicit and include r5 == 1 here, too.
Also -- where would you add the smp_mb__after_release_acquire to fix
(i.e. forbid) this? Immediately after cpu1()'s read of y?
> +Although cpu0(), cpu1(), and cpu2() will see their respective reads and
> +writes in order, CPUs not involved in the release-acquire chain might
> +well disagree on the order. This disagreement stems from the fact th...
2016 Jan 26
1
[v3,11/41] mips: reuse asm-generic/barrier.h
On Tue, Jan 26, 2016 at 11:19:27AM +0100, Peter Zijlstra wrote:
> On Mon, Jan 25, 2016 at 10:03:22PM -0800, Paul E. McKenney wrote:
> > On Mon, Jan 25, 2016 at 04:42:43PM +0000, Will Deacon wrote:
> > > On Fri, Jan 15, 2016 at 01:58:53PM -0800, Paul E. McKenney wrote:
> > > > On Fri, Jan 15, 2016 at 10:27:14PM +0100, Peter Zijlstra wrote:
>
> > > >
2016 Jan 26
1
[v3,11/41] mips: reuse asm-generic/barrier.h
On Tue, Jan 26, 2016 at 11:19:27AM +0100, Peter Zijlstra wrote:
> On Mon, Jan 25, 2016 at 10:03:22PM -0800, Paul E. McKenney wrote:
> > On Mon, Jan 25, 2016 at 04:42:43PM +0000, Will Deacon wrote:
> > > On Fri, Jan 15, 2016 at 01:58:53PM -0800, Paul E. McKenney wrote:
> > > > On Fri, Jan 15, 2016 at 10:27:14PM +0100, Peter Zijlstra wrote:
>
> > > >
2016 Jan 15
5
[v3,11/41] mips: reuse asm-generic/barrier.h
On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> So smp_mb() provides transitivity, as do pairs of smp_store_release()
> and smp_read_acquire(),
But they provide different grades of transitivity, which is where all
the confusion lays.
smp_mb() is strongly/globally transitive, all CPUs will agree on the order.
Whereas the RCpc release+acquire is weakly so, only the two
2016 Jan 15
5
[v3,11/41] mips: reuse asm-generic/barrier.h
On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> So smp_mb() provides transitivity, as do pairs of smp_store_release()
> and smp_read_acquire(),
But they provide different grades of transitivity, which is where all
the confusion lays.
smp_mb() is strongly/globally transitive, all CPUs will agree on the order.
Whereas the RCpc release+acquire is weakly so, only the two