search for: smlabb

On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

...t;) { diff --git a/celt/arm/celt_pitch_xcorr_arm.s b/celt/arm/celt_pitch_xcorr_arm.s index 09917b1..598e45b 100644 --- a/celt/arm/celt_pitch_xcorr_arm.s +++ b/celt/arm/celt_pitch_xcorr_arm.s @@ -309,7 +309,7 @@ xcorr_kernel_edsp_process4_done SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SML...

...bility=hidden -MT cb_search.lo -MD -MP -MF .deps/ cb_search.Tpo -c cb_search.c -o cb_search.o /var/folders/a9/a95y5WFFGOafslDBRmx2hk+++TM/-Tmp-//ccBD8xFa.s:375:no such instruction: `smulbb %edx,%ax,%si' /var/folders/a9/a95y5WFFGOafslDBRmx2hk+++TM/-Tmp-//ccBD8xFa.s:522:no such instruction: `smlabb %eax,%dx,%esi,%ecx' /var/folders/a9/a95y5WFFGOafslDBRmx2hk+++TM/-Tmp-//ccBD8xFa.s:555:no such instruction: `smlabb %ecx,%ax,%eax,%edx' /var/folders/a9/a95y5WFFGOafslDBRmx2hk+++TM/-Tmp-//ccBD8xFa.s:942:no such instruction: `smulbb %edi,%si,%ax' /var/folders/a9/a95y5WFFGOafslDBRmx2hk+...

...ons(-) diff --git a/celt/arm/celt_pitch_xcorr_arm.s b/celt/arm/celt_pitch_xcorr_arm.s index 09917b1..3c4b950 100644 --- a/celt/arm/celt_pitch_xcorr_arm.s +++ b/celt/arm/celt_pitch_xcorr_arm.s @@ -309,7 +309,7 @@ xcorr_kernel_edsp_process4_done SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SML...

...-I/root/dump/include -g -O2 -fvisibility=hidden -MT cb_search.lo -MD -MP -MF .deps/cb_search.Tpo -c cb_search.c -fPIC -DPIC -o .libs/cb_search.o fixed_arm5e.h: Assembler messages: fixed_arm5e.h:41: Error: no such instruction: `smulbb %ecx,%ax,%di' fixed_arm5e.h:50: Error: no such instruction: `smlabb %edx,%si,%edi,%ecx' fixed_arm5e.h:50: Error: no such instruction: `smlabb %edi,%cx,%esi,%edx' fixed_arm5e.h:41: Error: no such instruction: `smulbb %ecx,%si,%dx' fixed_arm5e.h:50: Error: no such instruction: `smlabb %esi,%dx,%ecx,%edi' fixed_arm5e.h:41: Error: no such instruction: `...

Hi I want to port speex to my pocket PC iPAQ1945 which has a Samsung processor 2410, an ARM9-based processor. I would like to write the specific optimized code for this chip. I had some experience at DSP chip and fixed-point coding but know nothing about embedded system and ARM. Could someone tell me some hint how to write optimized code for this pocket PC. If you can give me some links that will

Yes those instructions exist, although they're a bit slower than the basic 16x16->32 with 32-bit accumulation (SMLABB). So I'd be surprised if the function with 64 bit accumulation would run as fast as the current code. Don't know how much we care about 16-bit platforms. And accuracy should not matter. On the other hand, a 64-bit implementation is much cleaner/shorter, which is always a good argument :-...

Hi, I have one question: Will Speex run in realtime (both encode / decode probably simulateusly) on Nokia 6600 --- basicaly ARM9 104MHz with Symbian 7s after porting to its C++ or Java? I am thinking mostly about the worst quality encoding (optionally duplex). Can this processor make it? Oh 6600 has something about 6mb memory if I remember good. Plase cc kangur@polcom.net in replies.

...is, that might be the best solution. (It also allows you to discard the instruction if neither its result nor the Q flag is tested - you can't normally drop Q-flag-affecting instructions as they may be executed for side effects). There are similar issues with some other ARM instructions, e.g. SMLABB. Q is a sticky bit, like the floating-point cumulative exception flags, so the issues are a bit similar (the same issue would apply if e.g. you wanted to exploit floating-point hardware for integer division in a mode where the inexact exception was valid). You have the same issues of modelling th...

Hi all, I'm proposing integer saturation intrinsics. def int_ssat : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i32_ty]>; def int_usat : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i32_ty]>; The first operand is the integer value being saturated, and second is the saturation bit position. For scalar integer types, the semantics are: int_ssat: x <

...amp;r"(res) + : "%r"(b<<1),"r"(a), "r"(c) + ); + return res; +} + +/** 16x16 multiply-add where the result fits in 32 bits */ +#undef MAC16_16 +static inline opus_val32 MAC16_16(opus_val32 c, opus_val16 a, opus_val16 b) +{ + __asm__( + "smlabb %0, %1, %2, %0;\n" + : "=&r"(c), "=r"(a), "=r"(b) + : "0"(c), "1"(a), "2"(b) + ); + return c; +} + +/** 16x16 multiplication where the result fits in 32 bits */ +#undef MULT16_16 +static inline opus_val32 MULT16_16...

...ing mostly about the worst > quality encoding (optionally duplex). Can this processor make it? Oh 6600 > has something about 6mb memory if I remember good. I'm not sure the current code will do it (maybe?), but I think it can be done. On question: does this ARM support instruction like smlabb, smulbb, smulwb, ... ? Jean-Marc -- Jean-Marc Valin, M.Sc.A., ing. jr. LABORIUS (http://www.gel.usherb.ca/laborius) Université de Sherbrooke, Québec, Canada -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signatur...

...> Hi, > > Assuming you have gcc, you can already compile with --enable-arm5e-asm > and get good results. Right now, many places use ARM4 assembly even on > ARM5E, so if you want even better results, you can rewrite those. The > main instructions you'll want to use are smulbb, smlabb, smulwb and > smlawb, which aren't present in ARM4 and are usually more efficient than > mul, smull and mla. > > Jean-Marc >

...pus at xiph.org<mailto:opus at xiph.org>>, Marcello Caramma <mcaramma at cisco.com<mailto:mcaramma at cisco.com>> Subject: Re: [opus] Alleged bug in Silk codec Yes those instructions exist, although they're a bit slower than the basic 16x16->32 with 32-bit accumulation (SMLABB). So I'd be surprised if the function with 64 bit accumulation would run as fast as the current code. Don't know how much we care about 16-bit platforms. And accuracy should not matter. On the other hand, a 64-bit implementation is much cleaner/shorter, which is always a good argument :...

...t > > quality encoding (optionally duplex). Can this processor make it? Oh 6600 > > has something about 6mb memory if I remember good. > > I'm not sure the current code will do it (maybe?), but I think it can be > done. On question: does this ARM support instruction like smlabb, > smulbb, smulwb, ... ? > > Jean-Marc --- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project homepage: http://www.xiph.org/ogg/ To unsubscribe from this list, send a message to 'speex-dev-request@xiph.org' containing only the word 'unsubscribe' in the b...

...n. On Fri, Jun 20, 2014 at 9:46 AM, Jean-Marc Valin <jmvalin at jmvalin.ca> wrote: > Hi Marcello, > > Actually, we were careful to avoid the undefined behaviour here. In > fact, we are specifically running a clang test detecting undefined > behaviour. If you look at the silk_SMLABB_ovflw() macro, you will see it > is based on silk_ADD32_ovflw(), which is defined as: > > #define silk_ADD32_ovflw(a, b) ((opus_int32)((opus_uint32)(a) + > (opus_uint32)(b))) > > By casting to unsigned, all the cases are well defined. The cast back to > int is implementation-de...

Hello Greg If money isn't a problem Intel has an optimized compiler for eVC and XScale processors http://www.intel.com/software/products/compilers/techtopics/PCA_Optimization_WP.pdf If you have any luck getting the eVC compiler closer to realtime I'd really like to know. I'm still far from realtime when using Speex 1.1.3 on a HP iPAQ (Intel pxa255). Best regards Bjoern D.