search for: sm20

...nvdisasm prints >> identical output). Could you advise what the proper way of indicating >> that the memory is "global" to the op? I'm sure I'm just missing >> something simple. If you show me what to look for in SM35 I can >> probably find it on my own for SM20/SM30/SM50. > > Unfortunately this isn't something I know a lot about, so I'm going to > have do some research and get back to you, hopefully within a few days. Hi Robert, Were you able to find any further information out about this? Happy to provide with any traces or additional...

...oprietary driver does, however (and nvdisasm prints identical output). Could you advise what the proper way of indicating that the memory is "global" to the op? I'm sure I'm just missing something simple. If you show me what to look for in SM35 I can probably find it on my own for SM20/SM30/SM50. In case you're interested in looking at the mesa code, It's available on my atomic2 branch at: https://github.com/imirkin/mesa/commits/atomic2 . However I hardly expect you to debug my buggy code :) The SUREDP stuff is about surface RED ops, the existing code uses it but I'm...

...t 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: > Could you advise what the proper way of indicating > that the memory is "global" to the op? I'm sure I'm just missing > something simple. If you show me what to look for in SM35 I can > probably find it on my own for SM20/SM30/SM50. Sorry again for the delay. Here's what I've been able to find out about the generic thread address space (used by the SMs) and what types of memory it contains. Hopefully this clears things up. Local memory is a per-thread space. Shared memory is a per-CTA space (compute sha...

...>> identical output). Could you advise what the proper way of indicating > >> that the memory is "global" to the op? I'm sure I'm just missing > >> something simple. If you show me what to look for in SM35 I can > >> probably find it on my own for SM20/SM30/SM50. > > > > Unfortunately this isn't something I know a lot about, so I'm going to > > have do some research and get back to you, hopefully within a few days. > > Hi Robert, > > Were you able to find any further information out about this? Happy to &gt...

...:05:21PM -0400, Ilia Mirkin wrote: >> Could you advise what the proper way of indicating >> that the memory is "global" to the op? I'm sure I'm just missing >> something simple. If you show me what to look for in SM35 I can >> probably find it on my own for SM20/SM30/SM50. > > Sorry again for the delay. Here's what I've been able to find out about > the generic thread address space (used by the SMs) and what types of > memory it contains. Hopefully this clears things up. > > > Local memory is a per-thread space. > Shared m...

...s, however (and nvdisasm prints > identical output). Could you advise what the proper way of indicating > that the memory is "global" to the op? I'm sure I'm just missing > something simple. If you show me what to look for in SM35 I can > probably find it on my own for SM20/SM30/SM50. Unfortunately this isn't something I know a lot about, so I'm going to have do some research and get back to you, hopefully within a few days. > In case you're interested in looking at the mesa code, It's available > on my atomic2 branch at: > https://github.co...

...".version 2.2" +; RUN: llc < %s -march=ptx32 -mattr=ptx23 | grep ".version 2.3" ; RUN: llc < %s -march=ptx32 -mattr=sm10 | grep ".target sm_10" ; RUN: llc < %s -march=ptx32 -mattr=sm13 | grep ".target sm_13" ; RUN: llc < %s -march=ptx32 -mattr=sm20 | grep ".target sm_20" Index: lib/Target/PTX/PTX.td =================================================================== --- lib/Target/PTX/PTX.td (revision 130978) +++ lib/Target/PTX/PTX.td (working copy) @@ -38,6 +38,10 @@ "Use PTX Language Versi...

...nd i1 %0, %1 br i1 %3, label %then, label %else then: ; preds = %entry ret i32 1 else: ; preds = %entry ret i32 2 } Run like this: llvm-as test.ll -o test.bc llc -march=ptx -relocation-model=pic -mattr=sm20 -mattr=ptx22 -mattr=64bit -mattr=double test.bc -o test.ptx My first question would be why does it evaluate the entry basicblock twice (BB#0, BB#3), is this to do with predicated branching? If I run this through llc with the -debug=1 flag (or by viewing the graphs), I get this in the initial s...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index f010767..4a9e48f 100644 ---

...st/CodeGen/X86/2008-06-13-VolatileLoadStore.ll -mtriple=i686-linux -mattr=+sse2 | grep movl | /usr/local/google/home/blaikie/dev/llvm/build/clang/debug/bin/./count 2 -- Exit Code: 1 Command Output (stderr): -- Expected 2 lines, got 6. -- ******************** FAIL: LLVM :: CodeGen/NVPTX/convert-int-sm20.ll (16 of 51) ******************** TEST 'LLVM :: CodeGen/NVPTX/convert-int-sm20.ll' FAILED ******************** Script: -- /usr/local/google/home/blaikie/dev/llvm/build/clang/debug/bin/./llc < /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/NVPTX/convert-int-sm20.ll -march=nvptx...

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->