Displaying 1 result from an estimated 1 matches for "slotany".
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slogan
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
...}
def WriteALU : SchedWrite;
def WriteBranch : SchedWrite;
let SchedModel = MyTargetModel in {
// SLOT0 can handles everything
def Slot0 : ProcResource<1>;
// SLOT1 can't handles branches
def Slot1 : ProcResource<1>;
// Many micro-ops are capable of issuing on multiple ports.
def SlotAny : ProcResGroup<[Slot0, Slot1]>;
def : WriteRes<WriteALU, [SlotAny]> {
let Latency = 1;
let ResourceCycles =[1];
}
def : WriteRes<WriteBranch, [Slot0]> {
let Latency = 1;
let ResourceCycles =[1];
}
}
I've also changed OR1K.td to have
def : ProcessorModel<"g...