Displaying 10 results from an estimated 10 matches for "slot___".
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2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...gt; = TFRI 16777216; IntRegs:%vreg106
48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
This is not caught at this time, and only much later, when another
instruction is scheduled to __the same slot___ the old one "occupied" (48B),
the discrepancy is caught by one of unrelated asserts... I think at that
time there are simply some stale aliases in liveness table.
I'm going to continue with this tomorrow, but if this helps to identify a
lurking bug today, my day was worth it :) :) :)...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...%vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> This is not caught at this time, and only much later, when another
> instruction is scheduled to __the same slot___ the old one "occupied"
> (48B),
> the discrepancy is caught by one of unrelated asserts... I think at that
> time there are simply some stale aliases in liveness table.
>
> I'm going to continue with this tomorrow, but if this helps to identify a
> lurking bug today,...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...ntRegs:%vreg106
48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
This is not caught at this time, and only much later, when another
instruction is scheduled to __the same slot___ the old one "occupied" (48B),
the discrepancy is caught by one of unrelated asserts... I think at that
time there are simply some stale aliases in liveness table.
I'm going to continue with this tomorrow, but if this helps to identify a
lurking bug today, my day was worth it :) :) :)...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...vreg106
> 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> This is not caught at this time, and only much later, when another
> instruction is scheduled to __the same slot___ the old one "occupied"
> (48B), the discrepancy is caught by one of unrelated asserts... I think
> at that time there are simply some stale aliases in liveness table.
>
> I'm going to continue with this tomorrow, but if this helps to identify
> a lurking bug today, my...
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...ntRegs:%vreg106
48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
This is not caught at this time, and only much later, when another
instruction is scheduled to __the same slot___ the old one "occupied" (48B),
the discrepancy is caught by one of unrelated asserts... I think at that
time there are simply some stale aliases in liveness table.
I'm going to continue with this tomorrow, but if this helps to identify a
lurking bug today, my day was worth it :) :) :)...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...;def> = COPY %D2<kill>; DoubleRegs:%vreg29
>> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
>> IntRegs:%vreg37
>>
>> This is not caught at this time, and only much later, when another
>> instruction is scheduled to __the same slot___ the old one "occupied"
>> (48B), the discrepancy is caught by one of unrelated asserts... I think
>> at that time there are simply some stale aliases in liveness table.
>>
>> I'm going to continue with this tomorrow, but if this helps to identify
>> a lur...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...ll>; DoubleRegs:%vreg29
> >> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> >> IntRegs:%vreg37
> >>
> >> This is not caught at this time, and only much later, when another
> >> instruction is scheduled to __the same slot___ the old one
> "occupied"
> >> (48B), the discrepancy is caught by one of unrelated asserts... I
> >> think at that time there are simply some stale aliases in liveness
> table.
> >>
> >> I'm going to continue with this tomorrow, but if this he...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...%vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> This is not caught at this time, and only much later, when another
> instruction is scheduled to __the same slot___ the old one "occupied"
> (48B),
> the discrepancy is caught by one of unrelated asserts... I think at that
> time there are simply some stale aliases in liveness table.
>
> I'm going to continue with this tomorrow, but if this helps to identify a
> lurking bug today,...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
Andy,
I've described that issue (see below) when you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {