search for: sllw

...plication of either patterns or instruction definitions for RV32 and RV64. It's worth noting that RV64I is a different base ISA to RV32I. Rather than adding 64-bit operations, it re-defines the operations as 64-bit and introduces a small number of 'W' suffixed instructions such as ADDW, SLLW etc to operate on 32-bit values. There are some challenges though. Consider the variable-length shifts introduced in RV64I. SLLW, SRLW, and SRAW operate on 32-bit values and produce 32-bit sign-extended results. They read only the lower 5 bits from the shift amount. The following function should t...

..., but I don't think it's quite enough. Options include: 1. Only have one set of register definitions, and have the variable sized register class determine the bit width. The problem is there are often some instructions where I think you need to have registers modelled as subregisters. e.g. SLLW, ADDW etc in 64-bit RISC-V. These operate on 32-bit values and write the results sign-extended to the target 64-bit register. 2. Define both the 64-bit registers and the 32-bit subregisters, but make MatchRegisterName's behaviour change based on the HwMode. This works around the fact there are...

On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote: > > On 12/13/2018 6:25 AM, Alex Bradbury wrote: > > There's also likely to be cases where you want to calculate the demanded bits > > in order to determine if e.g. a W-suffixed instruction can be selected for > > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set