Displaying 5 results from an estimated 5 matches for "sllrr".
2010 Feb 08
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...ally two separate problems here. By way of example, what's happening is that the following pair of MBBs:
BB#315: derived from LLVM BB %bb
Predecessors according to CFG: BB#314
%reg1731<def> = SETHIi 1856
%reg1732<def> = ORri %G0, 1
%reg1733<def> = SLLrr %reg1732, %reg1729
%reg1734<def> = ORri %reg1731, 1
%reg1735<def> = ANDrr %reg1733, %reg1734
%reg1736<def> = SUBCCri %reg1735, 0, %ICC<imp-def>
BCOND <BB#3>, 9, %ICC<imp-use>
BA <BB#53>
Successors according to CFG...
2009 Dec 11
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
Hi, Chris
> That is target independent code, so you should not put sparc specific changes there. It sounds like one of the sparc-specific target hooks is wrong.
Since sparc does not provide any hooks for operation of branches (e.g.
AnalyzeBranch and friends) it might be possible that generic codegen
code is broken in absence of these hooks.
--
With best regards, Anton Korobeynikov
Faculty
2010 Feb 08
0
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...ertainly.
> - the above BB#315 immediately prior to output is
>
> BB#7: derived from LLVM BB %bb
> Live Ins: %L1 %L0 %L3 %L2 %L4
> Predecessors according to CFG: BB#6
> %L5<def> = SETHIi 1856
> %L6<def> = ORri %G0, 1
> %L3<def> = SLLrr %L6<kill>, %L3<kill>
> %L5<def> = ORri %L5<kill>, 1
> %L3<def> = ANDrr %L3<kill>, %L5<kill>
> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def>
> BCOND <BB#8>, 9, %ICC<imp-use,kill>
>...
2010 Feb 09
3
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...ove BB#315 immediately prior to output is
>>
>> BB#7: derived from LLVM BB %bb
>> Live Ins: %L1 %L0 %L3 %L2 %L4
>> Predecessors according to CFG: BB#6
>> %L5<def> = SETHIi 1856
>> %L6<def> = ORri %G0, 1
>> %L3<def> = SLLrr %L6<kill>, %L3<kill>
>> %L5<def> = ORri %L5<kill>, 1
>> %L3<def> = ANDrr %L3<kill>, %L5<kill>
>> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def>
>> BCOND <BB#8>, 9, %ICC<imp-use,...
2010 Feb 14
0
[LLVMdev] sparc status llvm 2.7?
...r to output is
>>>
>>> BB#7: derived from LLVM BB %bb
>>> Live Ins: %L1 %L0 %L3 %L2 %L4
>>> Predecessors according to CFG: BB#6
>>> %L5<def> = SETHIi 1856
>>> %L6<def> = ORri %G0, 1
>>> %L3<def> = SLLrr %L6<kill>, %L3<kill>
>>> %L5<def> = ORri %L5<kill>, 1
>>> %L3<def> = ANDrr %L3<kill>, %L5<kill>
>>> %L3<def,dead> = SUBCCri %L3<kill>, 0, %ICC<imp-def>
>>> BCOND <BB#8>, 9,...