Displaying 12 results from an estimated 12 matches for "slli".
Did you mean:
lli
2015 Jul 01
2
[LLVMdev] Match immediate value in tablegen
I was trying to do a pattern matching for a rd+imm instruction in my own
backend.
It looks something like:
def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16),
GPR:$src2>;
OR takes two i32 in registers and SLLI takes one i32 in registers and an
immediate.
But the immediate '16' does not work here and I tried different ways. May I
know if any of you have any idea how to bake an immediate value (16) into
the tablegen?
-----------...
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
...:$rs1, GPR:$rs2)>;
This pattern would match but is incorrect in the general case (e.g. if
rs1 is 0xffffffff and rs2 is 0x1, the result will be sign-extended).:
def : Pat<(udiv (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)),
(DIVUW GPR:$rs1, GPR:$rs2)>;
So this function would generate:
slli a1, a1, 32
srli a1, a1, 32
slli a0, a0, 32
srli a0, a0, 32
divu a0, a0, a1
ret
Rather than a simple divuw. Obviously we can argue whether such cases
are likely to occur in real-world code (certainly this specific case
of aext function args/returns isn't going to happen for
clang-generated code...
2017 Jul 27
2
GEP with a null pointer base
...t select, so here we see the second Select without a CMP:
BB#10: derived from LLVM BB %for.body.5
Predecessors according to CFG: BB#3 BB#9
%vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
//// <=== this SLLI clobbers FLAGS <============
%vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
BCC 2, <BB#12>, %FLAGS<imp-use>
Successors according to CFG: BB#11 BB#12
The problem is that Machine Code Sinking put an “SLLI" instruction...
2017 Jul 28
2
GEP with a null pointer base
...econd Select without a CMP:
>
> BB#10: derived from LLVM BB %for.body.5
> Predecessors according to CFG: BB#3 BB#9
> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>
> //// <=== this SLLI clobbers FLAGS <============
> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
> BCC 2, <BB#12>, %FLAGS<imp-use>
> Successors according to CFG: BB#11 BB#12
>
>
> The problem is that Machine Code Sinking...
2017 Jul 31
2
GEP with a null pointer base
...MP:
>>
>> BB#10: derived from LLVM BB %for.body.5
>> Predecessors according to CFG: BB#3 BB#9
>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>
>> //// <=== this SLLI clobbers FLAGS <============
>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>> BCC 2, <BB#12>, %FLAGS<imp-use>
>> Successors according to CFG: BB#11 BB#12
>>
>>
>> The problem is th...
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
As previously discussed in an RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the
RISC-V backend has i64 as the only legal integer type for the RV64 target.
Thanks to variable-sized register class support, this means there is no need
for duplication of either patterns or instruction definitions for RV32 and
RV64. It's worth noting that RV64I is a different base
2017 Jul 31
4
GEP with a null pointer base
...: derived from LLVM BB %for.body.5
>>> Predecessors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>;
>>> DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>;
>>> DataRegs:%vreg46,%vreg5
>>> BCC 2, <BB#12>, %FLAGS<imp-use>
>>> Successors according to CFG: BB#11 BB#12
>>>
>>...
2019 Feb 05
4
[RFC] Vector Predication
On 2/5/19 1:27 AM, Philip Reames via llvm-dev wrote:
>
> On 1/31/19 4:57 PM, Bruce Hoult wrote:
>> On Thu, Jan 31, 2019 at 4:05 PM Philip Reames via llvm-dev
>> <llvm-dev at lists.llvm.org> wrote:
>>> Do such architectures frequently have arithmetic operations on the
>>> mask registers? (i.e. can I reasonable compute a conservative
>>> length
2017 Aug 01
0
GEP with a null pointer base
...t;> BB#10: derived from LLVM BB %for.body.5
>>> Predecessors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>>> BCC 2, <BB#12>, %FLAGS<imp-use>
>>> Successors according to CFG: BB#11 BB#12
>>>
>>>
>&g...
2019 Feb 05
3
[RFC] Vector Predication
...:
>
> # args n in a0, dst in a1, a in a2, b in a3, AVL in t0
> foo:
> vsetvli a4, a0, vsew32,vlmul4 # vtype = 32-bit integer vectors, AVL in a4
> vlw.v v0, (a2) # Get 32b vector a into v0-v3
> vlw.v v4, (a3) # Get 32b vector b into v4-v7
> slli a5, a4, 2 # multiply AVL by element size 4 bytes
> add a2, a2, a5 # Bump pointer a
> add a3, a3, a5 # Bump pointer b
> vwmul.vv v8, v0, v4 # 64b result in v8-v15
>
> vsetvli zero, a0, vsew64,vlmul8 # Operate on 64b values, discard
>...
2019 Feb 01
3
[RFC] Vector Predication
On Fri, Feb 1, 2019 at 1:19 AM Bruce Hoult <brucehoult at sifive.com> wrote:
> On Thu, Jan 31, 2019 at 11:53 PM Luke Kenneth Casson Leighton via
> llvm-dev <llvm-dev at lists.llvm.org> wrote:
> >
> > ---
> > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> >
> > On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay
2017 Jul 24
2
GEP with a null pointer base
> On Jul 21, 2017, at 10:55 PM, Mehdi AMINI <joker.eph at gmail.com> wrote:
>
>
>
> 2017-07-21 22:44 GMT-07:00 Peter Lawrence <peterl95124 at sbcglobal.net <mailto:peterl95124 at sbcglobal.net>>:
> Mehdi,
> Hal’s transformation only kicks in in the *presence* of UB
>
> No, sorry I entirely disagree with this assertion: I believe we