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For example something like STARTUP ( http://wiki.osdev.org/Linker_Scripts#STARTUP) is not accepted by the LLVM LLD. :-/ On Wed, Apr 20, 2016 at 9:08 PM, Sky Flyer <skylake007 at gmail.com> wrote: > Yeah I found it, that's nice. Thanks a milion. > Could you please tell me how can I specify my bootstrap (startup code) in > the linking process? > > > On Wed, Apr 20, 2016 at 8:38 PM, Rafael Espíndola < > rafael.espindola at gmail.com> wrot...

search for VAStart. Cheers, Rafael On 20 April 2016 at 14:18, Sky Flyer <skylake007 at gmail.com> wrote: > Hi Rafael, > > Thanks a lot. > For example the start entry for me is 0x11000 by default which I don't know > where it come from! I thought there should be a default thing that sets this > entry address. > > On Wed, Apr 20, 2016 at 8:05 PM, Rafae...

...i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand"; let ParserMatchClass = CondCodeOperand; let DecoderMethod = "DecodePredicateOperand"; } James On Mon, 14 Dec 2015 at 13:44 Sky Flyer <skylake007 at googlemail.com> wrote: > But one question! > > imagine I define *cond* as a type of Xpred (Xpred:$cond) > and in the instruction, for instance *bits<6> cond*. > How can I assign the first i32imm to the 4 MSB of cond and the second > i32imm to the 2 LSB? :-/ > >...

...el On 20 April 2016 at 11:23, Sky Flyer via llvm-dev <llvm-dev at lists.llvm.org> wrote: > for instance, where is the internal default linker script located? How can I > change the default values, for example the star address... > > On Wed, Apr 20, 2016 at 5:17 PM, Sky Flyer <skylake007 at gmail.com> wrote: >> >> Hi all, >> >> How does the new lld implementation work with the "Linker Script" for the >> object file adjustment? >> I couldn't find enough resources on the web. Any help is highly >> appreciated. >> >&g...

...nnot use a function namly *getMnemonicAcceptInfo* > (mnemonic as input, and number of possible outputs as output), because > there are mnemonics that accepts different number of operands! :-/ > > Any help is highly appreciated. > > On Mon, Sep 28, 2015 at 10:53 AM, Sky Flyer <skylake007 at googlemail.com > <mailto:skylake007 at googlemail.com>> wrote: > > Hi all, > > in most of the architectures, assembly operands are comma-separated. > I would like to parse an assembly code that is space-separated and > I am having a bit of problem....

On Thu, Jul 23, 2015 at 9:53 AM, Sky Flyer <skylake007 at googlemail.com> wrote: > Hello all, > > I don't find anything helping me understand the llvm bang operator. In the > llvm TableGen language reference, it only says: > > 'TableGen also has “bang operators” which have a wide variety of meanings:' > > I would...

Hi all, in most of the architectures, assembly operands are comma-separated. I would like to parse an assembly code that is space-separated and I am having a bit of problem. In *ParseInstruction* function, I don't know what is the easiest way to figure out how many operands a mnemonic expected to have. In comma-separated assembly code, it just consuming commas (while

Hello all, I don't find anything helping me understand the llvm bang operator. In the llvm TableGen language reference, it only says: 'TableGen also has “bang operators” which have a wide variety of meanings: *'* I would be very thankful if someone can explain it to me. e.g. what does "!strconcat" or "!if" mean? Cheers ES -------------- next part --------------

Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32

Hi all, How does the new lld implementation work with the "Linker Script" for the object file adjustment? I couldn't find enough resources on the web. Any help is highly appreciated. Cheers, ES -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160420/dc5445e8/attachment-0001.html>

Thanks a lot Tim. I am getting an error which says: "LLVM ERROR: unable to write nop sequence of 0 bytes" Is there any way that I can print out the Obj code (I mean bitstream representation of the assembly code which is going to be placed in the ELF file), before making any ELF file? Cheers, ES On Tue, Oct 13, 2015 at 3:02 PM, Tim Northover <t.p.northover at gmail.com> wrote:

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7

Thanks Meador, The confusion point for me is that, does ! as an operator (bang operator) add any meaning to the strconcat? On Thu, Jul 23, 2015 at 5:25 PM, Meador Inge <meadori at gmail.com> wrote: > On Thu, Jul 23, 2015 at 9:53 AM, Sky Flyer <skylake007 at googlemail.com> > wrote: > > > Hello all, > > > > I don't find anything helping me understand the llvm bang operator. In > the > > llvm TableGen language reference, it only says: > > > > 'TableGen also has “bang operators” which have a wide...

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

Hi all, I have implemented AsmParser, CodeEmitter, and ELF object writing. AsmParser and CodeEmitter are tested and working fine, but I would like to see ELF objects build out of a parsed asm file. Is that possible? I tried this commands, but it didn't work corrctly: *llvm-mc -filetype=obj -arch=test file.s -o=a.o* and I think after an obj file is built, I should use this command but I am

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

Hi Krzystof, regarding your first solution (creating separate instruction), is it possible to somehow have cascading defm? for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit condition b, all in one instruction, instead of having one multiclass with 2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b" conditions, and the rest taken

Hi all, I try to run such a line in TableGen but seems it's not working. What is the problem with this code? multiclass cond { let Inst{1-0}=0b11 in defm fxy: ConditionalALU; .... } I receive this error: test.td:162:11: error: expected '=' in let expression let Inst{1-0}=0b11 in defm fxy: ConditionalALU; ^ -------------- next part -------------- An HTML

Hello all, I wan to ask, what is exactly the purpose of TSFlags and can it be used for the condition handling in instructions? How can I implement the conditions in the instruction when I don't have access to the Status Register? Best regards, ES -------------- next part -------------- An HTML attachment was scrubbed... URL:

Many thanks for your prompt reply. I mean, imagine you have 3 bits for condition flags in your instruction (e.g. overflow, zero, carry set, ...) for conditional executions AND there is no direct access to the Status Register, is it even possible to implement such scenario? On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 7/10/2015 9:32