search for: skx

...Skylake-era CPUs. See the thread at > https://lkml.org/lkml/2018/2/4/147 I'm strongly of the opinion that I think Arjan expressed: - retpoline alone is probably fine with sufficient RSB stuffing patches in the kernel - if some folks are worried about the security risk here and running on SKX, they should use IBRS. Given the speed of IBRS on SKX and the complexity & runtime hit of thunking ret, I really don't see a good motivation for us teaching the compiler how to do this. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.or...

On Wed, 2018-02-07 at 00:36 +0000, Chandler Carruth wrote: > > > > That would be __x86_indirect_thunk but the kernel doesn't use it. > > We use -mindirect-branch-register and only ever expect the compiler > > to use the register versions which are CET-compatible. > > > > However, in at least one case in the 32-bit kernel we do emit the > > old

Hey guys, I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. In the IR, we represent a 4b vector mask as <4 x i1>. This assumes that the storage container for this type is also 4b, but it's not. The smallest mask register on SKX is 8b. This also implies that the smallest load/store moves 8b. We run into problems w...

...> https://lkml.org/lkml/2018/2/4/147 > > > I'm strongly of the opinion that I think Arjan expressed: > > - retpoline alone is probably fine with sufficient RSB stuffing patches in > the kernel > - if some folks are worried about the security risk here and running on > SKX, they should use IBRS. > > Given the speed of IBRS on SKX and the complexity & runtime hit of > thunking ret, I really don't see a good motivation for us teaching the > compiler how to do this. > -------------- next part -------------- An HTML attachment was scrubbed... URL:...

After upgrading to xen unstable packages I'm seeing the following problem: skx@itchy:~$ sudo /etc/init.d/xend restart Restarting XEN control daemon: xendTraceback (most recent call last): File "/usr/lib/xen-3.0-unstable-1/bin/xend", line 40, in ? from xen.xend.server import SrvDaemon File "/usr/lib/python2.4/site-packages/xen/xend/server/SrvDaemon.py&qu...

On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> On Oct 20, 2016, at 8:54 AM, Cameron McInally via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hey guys, >> >> I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. >> >> In the IR, we represent a 4b vector mask as <4 x i1>. This assumes >> that the storage container for this type is also 4b, but it's not. > > The storage type is not relevant, these bits are “unreachable” from the IR point of v...

...security hole Xen versions 3.x, and 3.1 contain a tool for processing Xen trace buffer information. This tool uses the static file /tmp/xenq-shm insecurely allowing a local user to truncate any local file when xenbaked or xenmon.py are invoked by root. Sample session: # setup. skx at vain:~$ ln -s /etc/passwd /tmp/xenq-shm # later. skx at vain:~$ sudo xenbaked # all gone. :( skx at vain:~$ ls -l /etc/passwd -rw-r--r-- 1 0 root 327680 2007-10-17 00:14 /etc/passwd This flaw is known as CVE-2007-3919 by the common vulnerabilities and exposures project...

...2/4/147 >> >> >> I'm strongly of the opinion that I think Arjan expressed: >> >> - retpoline alone is probably fine with sufficient RSB stuffing patches >> in the kernel >> - if some folks are worried about the security risk here and running on >> SKX, they should use IBRS. >> >> Given the speed of IBRS on SKX and the complexity & runtime hit of >> thunking ret, I really don't see a good motivation for us teaching the >> compiler how to do this. >> > -------------- next part -------------- An HTML attachm...

...a llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi, >> >> I used clang -O3 -c -emit-llvm on the follow code to generate a bitcode, >> say a.bc. I read the .ll file and didn't see any gather intrinsic. Also, I >> used opt -O3 -mcpu=core-avx2/-mcpu=skx, but there is still no gather >> intrinsic generated. >> >> int foo(int A[800], int B[800], int C[800]) { >> for (int i = 0; i < 800; i++) { >> A[B[i]] = i + 5; >> } >> >> for (int i = 0; i < 800; i++) { >> A[B[...

...0, 2016 at 1:36 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Zhi, > On 20 January 2016 at 13:33, zhi chen <zchenhn at gmail.com> wrote: > > Thanks for your response. The attached is the .bc file after my pass. I > > could generate the assembly with -mcpu=skx but not with -mcpu=core-avx2. > > Could you please take a look? BTW, I am using LLVM-3.7. > > It seems to compile fine on trunk, so it looks like someone has > already fixed the bug. > > Tim. > -------------- next part -------------- An HTML attachment was scrubbed... URL: &...

Hi Tim, Thanks for your response. The attached is the .bc file after my pass. I could generate the assembly with -mcpu=skx but not with -mcpu=core-avx2. Could you please take a look? BTW, I am using LLVM-3.7. Best, Zhi On Wed, Jan 20, 2016 at 1:21 PM, Tim Northover <t.p.northover at gmail.com> wrote: > > Only typo that caught my eye is ‘llvm.masked.gather.v8f64’ which should > have v2 instead of v8 to...

...6 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: >>>> On Oct 20, 2016, at 8:54 AM, Cameron McInally via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>>> >>>> Hey guys, >>>> >>>> I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. >>>> >>>> In the IR, we represent a 4b vector mask as <4 x i1>. This assumes >>>> that the storage container for this type is also 4b, but it's not. >>> The storage type is not relevant, these bits are “unreacha...

I'm running a few servers sitting on top of a NetAPP file server ? everything runs great, but periodically I'm getting: nfs_getpages: error 13 vm_fault: pager read error, pid 11355 (https) errors on my screen ? not always same pid ? the annoying part is that it seems to always affect the same jail that is running .. if I shutdown all jails on that physical server, everything shuts down

Hi, I used clang -O3 -c -emit-llvm on the follow code to generate a bitcode, say a.bc. I read the .ll file and didn't see any gather intrinsic. Also, I used opt -O3 -mcpu=core-avx2/-mcpu=skx, but there is still no gather intrinsic generated. int foo(int A[800], int B[800], int C[800]) { for (int i = 0; i < 800; i++) { A[B[i]] = i + 5; } for (int i = 0; i < 800; i++) { A[B[i]]++; } for (int i = 0; i < 800; i++) { A[i] = B[C[i]];...

...n target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64 ________________________________ From: Do...

...n target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64 ________________________________ From: Do...

...1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, for the SKX architecture, many instructions that use only the lower registers of XMM0-XMM15 or YMM0-YMM15, can be encoded by either the EVEX or the VEX format. For such cases, using the VEX encoding results in a code size reduction of ~2 bytes even though it is compiled with the AVX512F/AVX512VL features enabl...

...Z' > note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, > silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, > westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, > core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, > cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, > athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, > barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, > znver2, > x86-64 > > > ---...

...ct: Re: [llvm-dev] how to force llvm generate gather intrinsic 1) I did not switch-on masked_load/store to AVX1, I can do this. 2) I did not switch-on masked gather on AVX2 because the instruction is slow. There is no scatter on AVX2. 3) Currently, gather/scatter does not work on SKX because the patch is still under review http://reviews.llvm.org/D15690. I’d be happy if you agree to review it. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Saturday, January 23, 2016 02:58 To: Sanjay Patel <spatel at rotateright.com<mailto:spatel at rotateright.com&...

...EX encoding format: > > [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] > > # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 > > > > Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take > only up to 3 bytes. > > Consequently, for the SKX architecture, many instructions that use only > the lower registers of XMM0-XMM15 or YMM0-YMM15, can be encoded by either > the EVEX or the VEX format. For such cases, using the VEX encoding results > in a code size reduction of ~2 bytes even though it is compiled with the > AVX512F/AVX...