Displaying 6 results from an estimated 6 matches for "skipinstruct".
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skip_instruct
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...egister(Reg)) {
for (MCRegUnitRootIterator Roots(Reg, &TRI); Roots.isValid(); ++Roots)
{
unsigned Root = *Roots;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Root),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {
const MachineInstr* MI = &*UI;
SlotIndex InstSlot =
LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot;
}
//for (MCSuperRegIterator Supers(Root, &a...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...ore quick question. in LiveIntervalAnalysis.cpp In
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx)
Did you really mean to use
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Reg),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {}
Aren't we currently dealing with units, not registers ?
SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
.and isn't MRI.use_nodbg_begin(Reg) expects a register, not a unit? .or did
I got it wrong again. Sorry to bug you on this.
Sergei
---
Qualcomm...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...; Roots.isValid();
> ++Roots) {****
>
> unsigned Root = *Roots;****
>
> for (MachineRegisterInfo::use_nodbg_iterator****
>
> UI = MRI.use_nodbg_begin(Root),****
>
> UE = MRI.use_nodbg_end();****
>
> UI != UE; UI.skipInstruction()) {****
>
> const MachineInstr* MI = &*UI;****
>
> SlotIndex InstSlot =
> LIS.getSlotIndexes()->getInstructionIndex(MI);****
>
> if (InstSlot > LastUse && InstSlot < OldIdx) ****
>
> LastUse = InstSlot;***...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
Hi Sergei, Andy,
Sorry - I got distracted with some other work. I'm looking into this and
PR13719 now. I'll let you know what I find out.
Sergei - thanks very much for the investigation. That should help me pin
this down.
Cheers,
Lang.
On Tue, Aug 28, 2012 at 2:33 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy, Lang,
>
> Thanks for the suggestion.
>
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...isterInfo.h:76
#6 0x086a8118 in llvm::MachineRegisterInfo::defusechain_iterator<true, true, false>::operator++ (this=0xbffff068) at /work/llvm/trunk/llvm/include/llvm/CodeGen/MachineRegisterInfo.h:514
#7 0x08803f51 in llvm::MachineRegisterInfo::defusechain_iterator<true, true, false>::skipInstruction (this=0xbffff068) at /work/llvm/trunk/llvm/include/llvm/CodeGen/MachineRegisterInfo.h:543
#8 0x0896d5bf in llvm::VirtRegAuxInfo::CalculateWeightAndHint (this=0xbffff0d8, li=...) at /work/llvm/trunk/llvm/lib/CodeGen/CalcSpillWeights.cpp:131
#9 0x0896d22e in llvm::CalculateSpillWeights::runOnMac...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
Andy, Lang,
Thanks for the suggestion.
I have spent more time with it today, and I do see some strange things in
liveness update. I am not at the actual cause yet, but here is what I got so
far:
I have the following live ranges when I start scheduling a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...