Displaying 2 results from an estimated 2 matches for "sizeop".
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2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...EC0, -128(r10)
ldd r0, -48(r10)
I am surprised that the BPF scalar instructions ldd and std use vector register
REGVEC0, which have type v8i64.
For example, the TableGen definition of the LOAD instruction taken from
BPFInstrInfo.td is:
class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
So I am surprised that the instruction selector finds as match for operand i64:$dst
the vector register REGVEC0, which has type v8i64 as defined below, inspired from
li...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...0, -48(r10)
>
> I am surprised that the BPF scalar instructions ldd and std use vector
> register
> REGVEC0, which have type v8i64.
> For example, the TableGen definition of the LOAD instruction taken from
> BPFInstrInfo.td is:
> class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
> : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
>
> So I am surprised that the instruction selector finds as match for operand
> i64:$dst
> the vector register REGVEC0, which has type v8i64 as defined...