search for: sitargetlow

...gt;; > > } // End Predicates = [isCIVI] > diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp > index a8f6ed5..4b6d118 100644 > --- a/lib/Target/AMDGPU/SIISelLowering.cpp > +++ b/lib/Target/AMDGPU/SIISelLowering.cpp > @@ -263,6 +263,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM, > setOperationAction(ISD::FDIV, MVT::f32, Custom); > setOperationAction(ISD::FDIV, MVT::f64, Custom); > > + // GCN CMP_SWAP needs input marshalling, and output demarshalling > + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

Hi, I've prepared patches for both LLVM and Clang to change the datalayout for R600. This may seem like a bold move, but I think it is warranted. R600/SI is a strange architecture in that it uses 64bit pointers but does not support 64 bit arithmetic except for load/store operations that roughly map onto getelementptr. The current datalayout for r600 includes n32:64, which is odd

...o it must be initialized after. > + if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { > + InstrInfo = new R600InstrInfo(*this); > + TLInfo = new R600TargetLowering(*this); > + } else { > + InstrInfo = new SIInstrInfo(*this); > + TLInfo = new SITargetLowering(*this); > + } > +} > + > +AMDGPUTargetMachine::~AMDGPUTargetMachine() > +{ > +} > + > +bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM, > + formatted_raw_ostream &Out, > +...