Displaying 3 results from an estimated 3 matches for "sischedule".
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2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...reg9
I have a feeling there is something wrong with my machine model in the
R600 backend, but I've experimented with a few variations of it and have
been unable to solve this problem. Does anyone have any idea what I
might be doing wrong?
Here are my resource definitions from lib/Target/R600/SISchedule.td
// BufferSize = 0 means the processors are in-order.
let BufferSize = 0 in {
// XXX: Are the resource counts correct?
def HWBranch : ProcResource<1>;
def HWExport : ProcResource<7>; // Taken from S_WAITCNT
def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
def HW...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...is example debugging output which. Where is the cycle time
here?
> BTW- I just checked in a small fix for in-order scheduling that might make debugging this easier.
>
I will take a look at this.
Thanks,
Tom
> Andy
>
> > Here are my resource definitions from lib/Target/R600/SISchedule.td
> >
> > // BufferSize = 0 means the processors are in-order.
> > let BufferSize = 0 in {
> >
> > // XXX: Are the resource counts correct?
> > def HWBranch : ProcResource<1>;
> > def HWExport : ProcResource<7>; // Taken from S_WAITCNT
&g...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...MDGPU/SIMachineFunctionInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
> llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
> llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
> llvm/trunk/lib/Target/AMDGPU/SISchedule.td
> llvm/trunk/lib/Target/AMDGPU/TargetInfo/
> llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/TargetInfo/CMakeLists.txt
> llvm/trunk/lib/Target/AMDGPU/TargetInfo/LLVMBuild.txt
> llvm/trunk/lib/Target/AMDGPU/TargetInfo/...