Displaying 2 results from an estimated 2 matches for "simplifyor".
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2013 Jun 04
3
[LLVMdev] Missing InstCombine optimization.
...; idx & -8
3. hi*8+lo -> hi*8 | lo
4. (idx & -8) | (idx & 7) -> idx & (-8 | 7) -> idx
After 155362 pattern #2 is deferred to DAGCombine stage, so InstCombine is unable to apply pattern #4:
4*. ((idx >> 3) << 3) | (idx & 7) -> idx // SimplifyOr can't handle it.
So now LLVM IR contains a couple of redundant operations:
%mul312 = shl nsw i32 %shr, 3 ; hi*8
%add313 = or i32 %mul312, %and ; hi*8 + lo == idx
These few additional operations over index prevent our analysis pass from recognizing memory access patterns and I believe coul...
2013 Jun 04
0
[LLVMdev] Missing InstCombine optimization.
...| lo
>
> 4. (idx & -8) | (idx & 7) -> idx & (-8 | 7) -> idx
>
>
>
> After 155362 pattern #2 is deferred to DAGCombine stage, so InstCombine is
> unable to apply pattern #4:
>
> 4*. ((idx >> 3) << 3) | (idx & 7) -> idx // SimplifyOr can’t handle
> it.
>
>
>
> So now LLVM IR contains a couple of redundant operations:
>
> %mul312 = shl nsw i32 %shr, 3 ; hi*8
>
> %add313 = or i32 %mul312, %and ; hi*8 + lo == idx
>
>
>
> These few additional operations over index prevent our analysis pass...