Displaying 6 results from an estimated 6 matches for "simplifydemandedvectorelt".
Did you mean:
simplifydemandedvectorelts
2019 Jan 31
4
[RFC] Vector Predication
...make this work
properly.
> My context for these questions is that my experience recently w/o
> existing masked intrinsics shows us missing fairly basic
> optimizations, precisely because they weren't able to reuse all of the
> existing infrastructure. (I've been working on
> SimplifyDemandedVectorElts recently for exactly this reason.) My
> concern is that your EVL proposal will end up in the same state.
I think that's just the nature of the beast. We need IR-level support
for masking and we have to teach LLVM about it.
-David
2019 Feb 01
2
[RFC] Vector Predication
...y context for these questions is that my experience recently w/o
>>> existing masked intrinsics shows us missing fairly basic
>>> optimizations, precisely because they weren't able to reuse all of the
>>> existing infrastructure. (I've been working on
>>> SimplifyDemandedVectorElts recently for exactly this reason.) My
>>> concern is that your EVL proposal will end up in the same state.
>> I think that's just the nature of the beast. We need IR-level support
>> for masking and we have to teach LLVM about it.
> I'm solidly of the opinion that...
2019 Jan 31
4
[RFC] Vector Predication
...ntext for these questions is that my experience recently w/o
> >> existing masked intrinsics shows us missing fairly basic
> >> optimizations, precisely because they weren't able to reuse all of the
> >> existing infrastructure. (I've been working on
> >> SimplifyDemandedVectorElts recently for exactly this reason.) My
> >> concern is that your EVL proposal will end up in the same state.
> > I think that's just the nature of the beast. We need IR-level support
> > for masking and we have to teach LLVM about it.
> I'm solidly of the opinion th...
2019 Jan 31
6
[RFC] Vector Predication
Hi,
There is now an RFC for a roadmap to native vector predication support
in LLVM and a prototype implementation:
https://reviews.llvm.org/D57504
The prototype demonstrates:
- Predicated vector intrinsics with an explicit mask and vector length
parameter on IR level.
- First-class predicated SDNodes on ISel level. Mask and vector length
are value operands.
- An incremental strategy
2019 Feb 01
2
[RFC] Vector Predication
...>
>> My context for these questions is that my experience recently w/o
>> existing masked intrinsics shows us missing fairly basic
>> optimizations, precisely because they weren't able to reuse all of the
>> existing infrastructure. (I've been working on
>> SimplifyDemandedVectorElts recently for exactly this reason.) My
>> concern is that your EVL proposal will end up in the same state.
> I think that's just the nature of the beast. We need IR-level support
> for masking and we have to teach LLVM about it.
I'm solidly of the opinion that we already *have*...
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
Sanjay,
I'm looking at some missed optimizations caused by D70246. Here's a test case:
define <4 x float> @f(i32 %t32, <4 x float>* %t24) {
.entry:
%t43 = insertelement <3 x i32> undef, i32 %t32, i32 2
%t44 = bitcast <3 x i32> %t43 to <3 x float>
%t45 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32>
<i32 0, i32 undef,