Displaying 6 results from an estimated 6 matches for "simode".
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imode
2018 Feb 07
2
retpoline mitigation and 6.0
...{
unsigned Reg = MO.getReg();
+ bool emit_pct = true;
+
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
@@ -384,6 +386,9 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, 32);
break;
+ case 'V':
+ emit_pct = false;
+ /* fall through */
case 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
@@ -391,7 +396,10...
2018 Feb 07
0
retpoline mitigation and 6.0
...bool emit_pct = true;
> +
> switch (Mode) {
> default: return true; // Unknown mode.
> case 'b': // Print QImode register
> @@ -384,6 +386,9 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
> MachineOperand &MO,
> case 'k': // Print SImode register
> Reg = getX86SubSuperRegister(Reg, 32);
> break;
> + case 'V':
> + emit_pct = false;
> + /* fall through */
> case 'q':
> // Print 64-bit register names if 64-bit integer registers are
> available.
> // Otherwise, pr...
2018 Feb 07
0
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 13:16 -0800, Guenter Roeck wrote:
> Here are my exact versions:
> llvm: 3afd566557f3 ("AMDGPU: Add 32-bit constant address space")
> clang: 848874aed95a ("[clang-format] Fix ObjC message arguments formatting.")
OK, mine are slightly newer than that now, but I now get a working 64-
bit defconfig build. It'll still break with any PV
2018 Feb 07
3
retpoline mitigation and 6.0
On Wed, Feb 07, 2018 at 08:44:32PM +0000, David Woodhouse wrote:
> On Wed, 2018-02-07 at 10:11 -0800, Guenter Roeck wrote:
>
> > On Wed, Feb 07, 2018 at 10:49:25AM +0000, David Woodhouse wrote:
> > > Hm, please could we also have the %V asm constraint modifier? That
> > > allows us to emit calls to the thunks from inline asm using the
> > > register that the
2018 Feb 07
0
retpoline mitigation and 6.0
...unsigned Reg = MO.getReg();
+ bool EmitPercent = true;
+
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
@@ -384,6 +386,9 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
MachineOperand &MO,
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, 32);
break;
+ case 'V':
+ EmitPercent = false;
+ LLVM_FALLTHROUGH;
case 'q':
// Print 64-bit register names if 64-bit integer registers are
available.
// Otherwise, print 32-bit register names.
@@ -391,7 +396,1...
2018 Feb 07
2
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 23:30 +0000, Chandler Carruth wrote:
> This should go to llvm-commits as a proper review. Do you want to do
> that David? Want someone on our end to pick it up?
I'll attempt to add some test cases...
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