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...I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r# is just enough for simd8 i32). Then the register allocator never need to go to allocate the sub-registers, just operate them as a whole. right? Yes, it looks really easy for divergent registers. But I think then I would lose the ability to allocate uniform register. Am I right? Is there any way to allocate uniform registe...

...(add (decimate (shl gpr_b, 1), 4)), (add (decimate (shl gpr_b, 2), 4)), (add (decimate (shl gpr_b, 3), 4))]>; // simd byte use stride 2 register as stride 1 does not support useful ALU instruction def gpr_b_simd8 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], [(add (decimate gpr_b, 16)), (add (decimate (shl gpr_b, 2), 16)), (add (decimate (shl gpr_b, 4), 16)),...

...n RegisterInfo.td. And I also have a question about the attached RegisterInfo.td file. Do I have to define different SubRegIndex like below to make TableGen works correctly? foreach Index = 0-15 in { def subd#Index :SubRegIndex<32, !shl(Index, 5)>; //used as SubRegIndex when declaring gpr_d_simd8 def subw#Index: SubRegIndex<16, !shl(Index, 4)>; //used as SubRegIndex when declaring gpr_w_simd8 ... } If anything I am not saying clear, just reply the mail. Thanks for any help! Thanks! Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://l...